>Why do they use the pads to connect the Top or Bottom layers with the >InternalPlane instead of using the via
�s? Which are do you think is the best >to use, the via
�s or the pad
�s? Because the example was written for an earlier verison of Protel that would only connect pads to the power plane and the example was never updated to the current version which connects pads and vias to the power plane. >through vias or pads, but I saw also the tracks that were connected on Top >and Bottom layers between VCC's and between GND's. Which Design Rules do I >need to setup to see only the vias or pads? I wish I knew. It gets annoying when the autorouter leaves a big fat trace through a section and it didn't have to. There is probably some combinations of routing topology that will reduce this, but everything I've tried has not quite done it. I'll run just the fan out route clean it up and lock all the preroutes and run the other routing steps and get fewer of these silly things, but I'll still have some. Rob "Vladimir Bozin" <[EMAIL PROTECTED]> on 05/14/2001 07:28:18 PM Please respond to "Protel EDA Forum" <[EMAIL PROTECTED]> To: "Protel EDA Forum" <[EMAIL PROTECTED]> cc: (bcc: Rob LaMoreaux/DSPT) Subject: [PEDA] Autorouter, via's and pad's
Hello! I am new to Protel and I would like to ask you questions regarding via
�s and pad
�s. The examples that Protel uses, specifically in the example of the 4 layers PCB (Top, Bottom, InternalPlane VCC, InternalPlane GND) they use pads to connect the Top or Bottom layer with the InternalPlane and use the via
�s to connect the Top and Bottom layers. Why do they use the pads to connect the Top or Bottom layers with the InternalPlane instead of using the via
�s? Which are do you think is the best to use, the via
�s or the pad
�s? The second question that I would like to ask is about the Autorouter. I used Autorouter to run four layers (Top, Bottom, VCC, GND) PCB. I was hoping to see the connections from Top (Bottom) to InternalPlane only through vias or pads, but I saw also the tracks that were connected on Top and Bottom layers between VCC's and between GND's. Which Design Rules do I need to setup to see only the vias or pads? Any help would be appreciated. Thank you. Vladimir Bozin * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/[email protected] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
