At 08:36 PM 6/12/01 -0500, you wrote:
>Of course I am using only a single 19-inch monitor, not two monitors as some
>do. But I think it is very tedious to correctly make all the changes while
>viewing both the schematic and the PCB at a scale where pin numbers and nets
>can be read while panning around the traces. True, I may be doing it wrong
>but the alternatives don't sound less error prone or less tedious either.
One of the alternatives I have suggested -- and which I have actually used
-- is neither error-prone nor is it tedious. And, especially, it does not
involve, in the end, renumbered pins, which are *really* an invitation to
error.
This is the option of using dummy parts. I did this with an FPGA with a
huge pile of interchangeable pins. I moved the swappable pins to a mech
layer, on the PCB, and placed single-pad dummy components on top of these
pins. These pads had designators that clearly indicated what pad they
represented. Then single-pin parts were dropped on top of the FPGA pins on
the schematic. This automatically wires them into the same net as the pin
they represent. Then the netlist was reloaded. The dummy parts now have the
original net assignments.
To rearrange them is just a matter of picking them up and moving them
around until the rat's nest looks good. They can also be moved at any
subsequent time. The board can be designed like this, and if one was in a
hurry, it could be left like this. But to be more thorough, the schematic
should be modified and the dummy parts removed. I highly recommend that pin
renumbering on the PCB not be used for swapping. Not only is it tedious,
but it is inherently not checkable except manually, looking at every pin.
Making a new schematic symbol that implements the swaps made on the PCB is
better; still better is rearranging parts of a multipart component (as I
recommend with resistor packs) or rewiring (which is easiest if it merely
involves the change of a signal name on a resistor pack pin).
It is *easy*; if it does not seem easy, it has not been understood. It is
actually harder to describe than it is to do, once the procedure has been
understood.
When I was done with the FPGA, I simply looked at the footprint and noted
what dummy parts were sitting on what original pins. Even though there were
a hundred pins involved, it was so fast to make a list of equivalents in
order that I did not bother with such procedures as generating a net list.
Instead I just went back to the schematic and made the changes (I think I
had net names sitting on the FPGA pins, so changing them was just a matter
of picking up the labels and shuffling them around according to the written
list I had.)
Likewise, if it had been resistor pack pins, and the resistors, say they
were pull-ups, were represented by individual sections, it would have just
been a matter of picking up the sections and moving them around.
[EMAIL PROTECTED]
Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433
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