Maybe PROTEL could offer some comments on this....
> -----Original Message-----
> From: Brad Velander [mailto:[EMAIL PROTECTED]]
> Sent: Friday, June 22, 2001 11:49 AM
> To: 'Protel EDA Forum'
> Subject: Re: [PEDA] DRC for via sizing. Was: enhancements:
>
>
> HuH?
> Well I tried that report function on the vias that you mention
> Abd-ul Rahman, it certainly doesn't make any sense to me because I just
> tried it on a board that has an outline and components entered but no
> routing done. It does report my Routing Via Style for the size however, it
> reports a via count of 30 when there were absolutely no vias in the design
> yet. None in component footprints either. So again I state, huh?
>
> As for the Routing Via Style check in the DRC rules, the text
> comments in the upper right of the DRC window state "The maximum
> and minimum
> via attributes are checked by the on-line and batch DRC."
> Obviously another
> in the long list of Protel lies.
>
> Brad Velander,
> Lead PCB Designer,
> Norsat International Inc.,
> #300 - 4401 Still Creek Dr.,
> Burnaby, B.C., V5C 6G9.
> Tel. (604) 292-9089 direct
> Fax (604) 292-9010
> website www.norsat.com
>
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