Hello Alistair, the boot I/O state of the port G lines is set inside the kernel options. If you issue the command: make kernelconfig starting from the devboard-R2_01 directory.
Navigating in the menu: "Drivers for ETRAX 100LX built-in interfaces" you will find an option called: "Port G Output". There you can set the startup state of the G0, G8-G15, G16-G23 and G24 I/O pins. In general when the Fox VHDL is mounted on the Fox Board you cannot program the FPGA using the 2x5 Jtag header onboard the Fox VHDL for conflict with the PortG lines. But reversing the data programming lines is not enough to let you use the JTAG header since the signal Jtag TRST is connected to the Fox Board Og25 that is a only-output pin. So to be able to use the JTAG header to reprogram the FPGA you should disconnect the Fox VHDL from the Fox Board or try to put the Fox Board in reset state closing the jumper J9 on the Fox Board. On the new coming Fox VHDL2 we provided a separate jumper to decouple the Jtag programming from the Fox Board. Best regards, Roberto Asquini Alistair ha scritto: > > Is there anyway to default the 32bit port G on the fox board to > be inputs rather than an outputs when using the foxbone bus? > > At boot the bus is currently loading my FPGA programming pins. There > is a good reason for me to do this..honestly. > > If the port G were inputs at power up then that would be great. After > the foxboard has booted I can control port G. But I just want to set > the direction in the Kernel so this is the case at power up. > > Any thoughts gratefully received. > > Great product by the way. It has really got me into embedded linux. > > Thanks again, > Alistair > > -- Roberto Asquini Acme Systems srl [EMAIL PROTECTED] http://www.acmesystems.it
