Hi Sven, > And no one said that it is. But points like table based exception > handling and section based threadvars can be relatively easily > achieved and benefits more targets while working on the optimizer > usually is a per platform work.
I agree that this very likely will make a big boost. From what I recall, and the oldest ARM platform we have (Marvell Kirkwood), every access to threadvars right now involve a full CPU cache flush (but forgot why exactly, has been a long time). Cheers, Simon _______________________________________________ fpc-devel maillist - fpc-devel@lists.freepascal.org http://lists.freepascal.org/cgi-bin/mailman/listinfo/fpc-devel
