I can only reproduce this with peephole optimization turned on (O2). Can
you share more code that reproduces it?
Either way here's a patch that might fix it?
Best Regards,
Jeppe
On 2/3/19 5:31 PM, Michael Ring wrote:
Forgot to mention I am using Trunk compiler from today revision 41187
ond optimization level was -O1
Michael
Am 03.02.19 um 17:20 schrieb Michael Ring:
I think I found another issue with Code generation, this time on
Cortex-M4:
I need to write Byte Aligned to the Data Register of the SPI
Interface of a STM32 Chip....
so what I (try) to do is:
using pByte(@DR)^ to force a single byte transfer and I succeed with
the byte alignment.......
BUT
please check the generated assembler, the requirred LSRS (SHR) is not
done by the compiler.
Just for fun I removed the byte alignment and the LSRS shows up...
@Jeppe, can this have to do with the fix for Cortex-M0 you provided
to me a few days ago or is this just another issue?
pByte(@DR)^ := aWord shr 8;
0800 185A LDR R0, [R11, #-0x38]
0800 185E ADD.W R1, R0, #0xC
0800 1862 LDRH R0, [R11, #-0x30]
0800 1866 STRB R0, [R1]
DR := aWord shr 8;
0800 1868 LDRH R0, [R11, #-0x30]
0800 186C LSRS R1, R0, #8
0800 186E LDR R0, [R11, #-0x38]
0800 1872 STR R1, [R0, #0xC]
Thank you,
Michael
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Index: compiler/arm/aoptcpu.pas
===================================================================
--- compiler/arm/aoptcpu.pas (revision 41233)
+++ compiler/arm/aoptcpu.pas (working copy)
@@ -1968,6 +1968,7 @@
strb reg1,[...]
}
if MatchInstruction(p, taicpu(p).opcode, [C_None], [PF_None]) and
+ (taicpu(p).ops=2) and
GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
MatchInstruction(hp1, A_STR, [C_None], [PF_B]) and
assigned(FindRegDealloc(taicpu(p).oper[0]^.reg,tai(hp1.Next))) and
@@ -1993,6 +1994,7 @@
uxtb reg3,reg1
}
else if MatchInstruction(p, A_UXTB, [C_None], [PF_None]) and
+ (taicpu(p).ops=2) and
GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
MatchInstruction(hp1, A_UXTH, [C_None], [PF_None]) and
(taicpu(hp1).ops = 2) and
@@ -2016,6 +2018,7 @@
uxtb reg3,reg1
}
else if MatchInstruction(p, A_UXTB, [C_None], [PF_None]) and
+ (taicpu(p).ops=2) and
GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
MatchInstruction(hp1, A_UXTB, [C_None], [PF_None]) and
(taicpu(hp1).ops = 2) and
@@ -2039,8 +2042,8 @@
uxtb reg3,reg1
}
else if MatchInstruction(p, A_UXTB, [C_None], [PF_None]) and
+ (taicpu(p).ops=2) and
GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
- (taicpu(p).ops=2) and
MatchInstruction(hp1, A_AND, [C_None], [PF_None]) and
(taicpu(hp1).ops=3) and
(taicpu(hp1).oper[2]^.typ=top_const) and
@@ -2075,6 +2078,7 @@
strh reg1,[...]
}
if MatchInstruction(p, taicpu(p).opcode, [C_None], [PF_None]) and
+ (taicpu(p).ops=2) and
GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
MatchInstruction(hp1, A_STR, [C_None], [PF_H]) and
RegEndofLife(taicpu(p).oper[0]^.reg,taicpu(hp1)) and
@@ -2100,6 +2104,7 @@
uxth reg3,reg1
}
else if MatchInstruction(p, A_UXTH, [C_None], [PF_None]) and
+ (taicpu(p).ops=2) and
GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
MatchInstruction(hp1, A_UXTH, [C_None], [PF_None]) and
(taicpu(hp1).ops=2) and
@@ -2126,6 +2131,7 @@
uxth reg3,reg1
}
else if MatchInstruction(p, A_UXTH, [C_None], [PF_None]) and
+ (taicpu(p).ops=2) and
GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
MatchInstruction(hp1, A_AND, [C_None], [PF_None]) and
(taicpu(hp1).ops=3) and
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