Is there some really good article (better than the wikipedia
https://en.wikipedia.org/wiki/Memory_barrier) on
- memory barrier
vs
- cache coherency
vs
interlocked
?
On 22/08/2020 16:57, Jonas Maebe via fpc-devel wrote:
Very important: InterlockedExchange is not a memory barrier, except on
x86.
It's not a semaphore/signal, it's just a field. It will never be
instantaneous since it can only have an effect once the target thread
actually tries to read it. Wrapping it in a bunch of synchronisation
primitives will make the whole system slower with no real benefit.
I guess the "Terminate" field is actually about cache coherency.
But I could not find any reliable info, if
- a memory barrier is needed for cache coherency.
- a memory barrier even affects cache coherency
I would assume that InterLocked will make sure (maybe as side effect)
that there is cache coherency ?
I.e. it makes sure (on all platforms) that the particular value that it
did set, will be immediately visible to all other threads (if they use
interlocked.... to read it)?
At least that is what I always thought. If that is not the case, I have
a lot of code to fix...
I acknowledge that
- a value set with InterlockedExchange by one thread
- may not be visible in other threads, if the access it *without*
InterlockedExchange
- does not affect the visibility of any other memory between threads.
How far off am I ?
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