Am 03.02.21 um 22:36 schrieb J. Gareth Moreton via fpc-devel:
On 03/02/2021 21:18, Florian Klämpfl via fpc-devel wrote:
Am 03.02.21 um 22:14 schrieb J. Gareth Moreton via fpc-devel:
Rats, I might have messed up with some of the arithmetic, as well as the dangers of crossing bitwise with logical Boolean operations, although some combinations still work - if the conditions are "x = 0" rather than "x <> 0" in the example:

      testq    %rbx,%rbx
      seteb    %al
      testq    %rsi,%rsi
      seteb    %dl
      andb     %dl,%al

Then this would equate to:

      orq      %rbx,%rsi
      seteb    %al

Indeed:

# [6] b:=(x=0) and (y=0);
    orl    %edx,%eax
# Var b located in register al
    seteb    %al

:)

Suddenly I'm feeling embarrassed!  I'll have to look up to see how that one is optimised!

Mistake aside, I'm looking for acceptable solutions for a platform-dependent node transformation, like a flag of some kind ($if defined etc. might get untidy, although is an option).


This depends on the transformation. Most transformations are beneficial for all platforms.
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I'll look around to see if there are other possible optimisations that revolve around DeMorgan's Laws first.  For "b:=(x<>0) and (y<>0);", there might not be a simple transformation available after all because, generally, bitwise not <> logical not.

I am pretty sure we miss some of the bit fiddeling stuff listed here: https://en.wikipedia.org/wiki/Bitwise_operation#Boolean_algebra

But there are more, like (typical pattern in the sha algorithm, I think I have even an unfinished patch for this one):

(a and b) or (c and not(b)) => c xor ((c xor a) and b)

One operation less and no additional temp. needed. Some googling might reveal more.

The main question regarding transformations is that there might be a place for "nor" and "nand" operations (more traditional operations for electronics since you can make circuits that do all the basic Boolean operations using just NOR and NAND gates... e.g. a NAND gate where both inputs are wired to the same signal becomes a NOT gate), and Intel does have "and not" (ANDN) as a single instruction on later processors (anything that supports BMI1).

Those can be done normally one the fly during code generation,
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