It seems Daniel C. Sobral wrote: > On the code: > > > ireason = inb (ata->port + AR_IREASON); > > ac->result.status = inb (ata->port + AR_STATUS); > > phase = (ireason & (ARI_CMD | ARI_IN)) | > > - (ac->result.status & ARS_DRQ); > > + (ac->result.status & (ARS_DRQ|ARS_BSY)); > > if (phase == PHASE_CMDOUT) > > break; > > DELAY (10); > > The missing delay is not relevant. (Or, at least, I hope acd is not > missing delays in wait loops!) > > The problem is the ARS_BSY signal. If my memory doesn't fail me, if > ARS_BSY is active, then the other signals may contain trash. In this > particular loop, ARS_BSY could be active, but it wasn't being > checked for, on the assumption that ARS_DRQ would only be up (down?) > when the operation completed.
This has been in there for ages, if the PR is still open it should be closed. Be patient though, I'm working as much as I can on the (really) new subsystem, and I hope to release the first snaps soon... -Søren To Unsubscribe: send mail to majord...@freebsd.org with "unsubscribe freebsd-current" in the body of the message
