Alexander Motin wrote:
> Adrian Chadd wrote:
>> .. erm, sys/mips/mips/machdep.c:
>>
>> /*
>> * call platform specific code to halt (until next interrupt) for the idle
>> loop
>> */
>> void
>> cpu_idle(int busy)
>> {
>> KASSERT((mips_rd_status() & MIPS_SR_INT_IE) != 0,
>> ("interrupts disabled in idle process."));
>> KASSERT((mips_rd_status() & MIPS_INT_MASK) != 0,
>> ("all interrupts masked in idle process."));
>>
>> if (!busy) {
>> critical_enter();
>> cpu_idleclock();
>> }
>> __asm __volatile ("wait");
>> if (!busy) {
>> cpu_activeclock();
>> critical_exit();
>> }
>> }
>>
>> .. does that look right?
>
> Yes it does. x86 does the same, but with more details. The general idea
> of the critical section is to block context switch out of idle thread
> until missed time events will be handled inside cpu_activeclock().
I was wrong. That's not good. I have no idea about mips wait instruction
semantics, related to disabling interrupts. In x86 semantics proper
solution is:
disable_intr();
if (sched_runnable())
enable_intr();
else
__asm __volatile("sti; hlt");
It makes interrupts enabled atomically with entering sleep state, that
closes race window and prevents entering into sleep after receiving
interrupt.
--
Alexander Motin
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