I have a patch to teach the PCI bus code and PCI-PCI bridge driver to manage 
PCI bus numbers.  The approach is somewhat similar to how NEW_PCIB manages I/O 
windows for briges.  Each bridge creates an rman to manage the bus numbers for 
all buses and bridges that live below it.  Each bus allocates a bus resource 
from its parent bridge, and child bridges allocate their ranges from their 
parent devices.  At the "top" of the PCI tree, the Host-PCI bridges allocate 
their respective bus ranges from their PCI domain/segment.  There isn't really 
a device node for PCI domains, so I created a helper API that basically auto-
creates a PCI bus rman for each domain on first use and then sub-allocates 
from that for Host-PCI bridges.

The current patch (with some extra debugging) is at 

I would like to commit this to HEAD soon but thought I would post it for some 
pre-commit testing for the brave. :)  If you are really brave, try booting 
with 'hw.pci.clear_buses=1' which will force the kernel to renumber all buses 
in the system.  If you are really, really brave, try booting with 
'hw.pci.clear_bars=1', 'hw.pci.clear_buses=1', and 'hw.pci.clear_pcib=1'.  (My 
laptop survives with all those set)

Note that the patch only enables bus number management on amd64 and i386.  I 
believe ia64 just needs to define PCI_RES_BUS for this to work since it 
mandates ACPI.  Porting this to other platforms requires handling PCI_RES_BUS 
rseources for Host-PCI bridges in bus_alloc_resource(), bus_adjust_resource(), 
and bus_release_resource().

John Baldwin
freebsd-current@freebsd.org mailing list
To unsubscribe, send any mail to "freebsd-current-unsubscr...@freebsd.org"

Reply via email to