On Thu, Jan 08, 2015 at 05:09:23PM +0100, Micha?? Stanek wrote:
> Hello all,
> 
> I ran into an issue with AHCI BAR allocation on arm64. The AHCI PCI driver
> in sys/dev/ahci/ahci_pci.c assumes that ABAR (AHCI Base Address) register
> is located at offset 0x24 (BAR5) in the PCI header. Specification for AHCI
> confirms this is indeed the default address of the main BAR.
Yes, at least rev. 1.3 of AHCI just states that ABAR must be at offset 0x24.

> However, if
> AHCI uses 64-bit base addresses, then this register consists of two dwords
> starting at offset 0x20 - BAR4 and BAR5. This is the case on our arm64
> target and possibly other platforms using 64-bit BARs for AHCI.
Is it specified anywhere, or just a quirk of the specific implementation ?
If it is a quirk, would it make sense to also check the vendor or device
id before applying the logic ?

> 
> The following patch adds a check for the extended BAR in ahci_pci_attach()
> and sets the 'rid' in bus_alloc_resource_any accordingly. It fixes the
> allocation error on our platform.
> 
> Please review and test this patch on other platforms. If there are no
> issues then it will be committed in a week.
> 
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