FreeBSD_HEAD_amd64_gcc4.9 - Build #852 - Fixed:

Build information:
Full change log:
Full build log:

Change summaries:

291495 by bdrewery:
libllvmmirparser and libllvmlibdriver are only used in usr.bin/clang/llc and
usr.bin/clang/llvm-ar, respectively, when MK_CLANG_EXTRAS is yes.

MFC after:      1 week
Sponsored by:   EMC / Isilon Storage Division

291494 by rrs:
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's 
have been
tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still 
to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune
guide (for the hacked up version I just made it so I could run the -T option). 
Skylake CPU is not yet available (even though Intel is advertising it .. 
imagine that).
The Skylake PMC's will need to be tested once we can get a sample skylake CPU 

Sponsored by: Netflix Inc.

291493 by avos:
wpi: ignore ic_update_promisc() call when device is not running

This change will fix kernel panic with uninitialized (zeroed)
RXON structure.

Tested with Intel 3945BG, IBSS mode.

Approved by:    adrian (mentor)
Differential Revision:

291492 by mmel:
ARM: create new memory attribute for writethrough cacheable memory.
- add new TEX class for WT cacheable memory
- export new TEX class to kernel as VM_MEMATTR_WT attribute
- add new aliases VM_MEMATTR_WRITE_COMBINING and
  VM_MEMATTR_WRITE_BACK, it's used in DRM code

 Only Cortex A8 supports WT caching in HW. On rest of Cortex CPUs,
 WT requests is treated as uncacheable.

Approved by:    kib (mentor)

291491 by ngie:
Fix the build after ifconfig was converted over to lib80211 in r291470

Reported by: jenkins, O. Hartmann <>
Pointyhat to: adrian

291488 by arybchik:
sfxge: avoid TSO packets collapses bacause of not 2K aligned data

Sponsored by:   Solarflare Communications, Inc.
MFC after:      2 days
Differential Revision:

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