:Sounds like we need to smack whoever made your chipset as well.  Intel 
:learned their lesson (finally) with later revisions of the PIIX4.  I'm 
:guessing you're running this against a ServerWorks system.

atapci0: <ServerWorks ROSB4 ATA33 controller> port 0x8b0-0x8bf at device 15.1 on

    Uh huh.

    It might be possible to detect the situation during init-time by 
    explicitly looking for a reverse indexed time in a tight loop of 
    maybe a thousand reads, but that would still leave us with a statistical
    chance of not guessing right.

:Interesting.  This would be reasonably robust in the ripple-counter case 
:we have to deal with on the old PIIX4.  Have you tried implementing the 
:above yet, or measuring how much it costs?
:At any rate, please let me know for sure whether you're running on a 
:ServerWorks board, and I'll see if I can't find a Big Stick to hit them 

    I haven't measured the cost (extra loops) but I expect it would stabilize
    in no more then one additional loop, which would be three counter reads
    total or roughly the same as your originaln _safe code in the worst case.

    I think we could default to the _safe version and then explicitly change
    it to use the fast version if we see specific chipsets which we know
    to be good.


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