I have an idea in regards to the page-zero issue.  Presumably we want
    to avoid doing an IPI to every cpu to clear the TLB, so what we do
    instead is create a lazy TLB clearing mechanism based on the thread.
    The scheduler detects the request when it switches the thread in and
    invalidates the TLB.  Like this:

pmap_zero_page(vm_page_t m)
        vm_offset_t phys = VM_PAGE_TO_PHYS(m);

        if (*CMAP2)
                panic("pmap_zero_page: CMAP2 busy");
        critical_enter();                               <<<<<<<<<
        *CMAP2 = PG_V | PG_RW | phys | PG_A | PG_M;     <<<<<<<<<
        invltlb_1pg((vm_offset_t)CADDR2);               <<<<<<<<<
        curthread->td_lazytlb = PCPU_GET(cpumask);      <<<<<<<<<
        critical_exit();                                <<<<<<<<<

#if defined(I686_CPU)
        if (cpu_class == CPUCLASS_686)
                bzero(CADDR2, PAGE_SIZE);
        *CMAP2 = 0;

    Then we mod the scheduler to check td_lazytlb against PCPU_GET(cpumask)
    when it switches a thread in.  If the bit is not set it clears the TLB
    and sets the bit.

    Now, obviously the above is all just pseudo code.  We would want to
    properly abstract the API and fields, but I think it solves the problem
    quite nicely, at least in concept.


:peter       2002/07/08 16:09:11 PDT
:  Modified files:
:    sys/vm               vm_zeroidle.c 
:  Log:
:  Turn the zeroidle process off for SMP systems, there is still a possible
:  TLB problem when bouncing from one cpu to another (the original cpu will
:  not have purged its TLB if the it simply went idle).
:  Pointed out by:  [EMAIL PROTECTED]
:  Approved by:    Tor is never wrong. :-)
:  Revision  Changes    Path
:  1.12      +4 -0      src/sys/vm/vm_zeroidle.c

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