In message: <[EMAIL PROTECTED]>
Dirk-Willem van Gulik <[EMAIL PROTECTED]> writes:
: > So something in the cardbus_init() may be needed ?
:
: A full powercycle seems to change the situation; and does allow for the
: card(s) to work with just the csc/func calls.
I'm very confused now. I took a look at the datasheet to see how
calling cardbus_init() could have had any effect...
brgcntl = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
brgcntl |= CB_BCR_WRITE_POST_EN | CB_BCR_MASTER_ABORT;
pci_write_config(dev, CB_PCI_BRIDGE_CTRL, brgcntl, 2);
The CLPD6729 has a Type 0 header. The effect of these lines are to
turn on bits 5 and 7 in the MIN_GNT register (minimum grant time of
40us). I don't see how this happens.
pci_write_config(dev, CB_PCI_LEGACY16_IOADDR, 0, 2);
According to the datasheet, offset 0x44 is past the registers defined
(0-0x3f).
pci_write_config(dev, CB_PCI_MEMBASE0, 0, 4);
pci_write_config(dev, CB_PCI_MEMLIMIT0, 0, 4);
pci_write_config(dev, CB_PCI_MEMBASE1, 0, 4);
pci_write_config(dev, CB_PCI_MEMLIMIT1, 0, 4);
pci_write_config(dev, CB_PCI_IOBASE0, 0, 4);
pci_write_config(dev, CB_PCI_IOLIMIT0, 0, 4);
pci_write_config(dev, CB_PCI_IOBASE1, 0, 4);
pci_write_config(dev, CB_PCI_IOLIMIT1, 0, 4);
This writes 0's 0x20-0x38. This is BAR4, BAR5, CardBus CIS, subsystem
id, expansion ROM, CAP ptr and some reserved registers that the
datasheet says nothing about. Some of these are read-only even.
So after the first power cycle, can you reboot w/o a power cycle?
Warner
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