The TSCs for each individual cpu core can drift relative to each other, even on multi-core chips like AMD X2s. This only effects code which uses the TSC, which isn't a whole lot. They need to be synchronized with each other (by calculating the drift and correcting for it) when using the TSC to log events, such as KTR logging might do. Since the TSC runs off the PLL, the drift rate will change based on the temperature of each core.
I'm not sure whether the LAPIC timers can be depended upon to operate from the same physical clock source or not (i.e. whether they drift relative to each other or not). I haven't tested them for that. -Matt _______________________________________________ freebsd-hackers@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-hackers To unsubscribe, send any mail to "[EMAIL PROTECTED]"