> What sync operation are you doing? At least for PREREAD or PREWRITE, > I'd expect any dirty cache lines to be flushed to RAM. If this isn't > happening, then you may want to submit a bug report.
For a PREREAD, I don't believe that it's correct to flush a dirty cache line to RAM. That would overwrite whatever had been DMA'ed into that cache line. What about the following procedure for a PREREAD for a non-cache aligned buffer I'll call dma_buf 1) read the entire cache line into a buffer, buf1 2) issue the invalidate 3) copy the portion of buf1 that preceeds dma_buf back to that address One problem I can see immediately is that there is a race here: if something tries to access the memory preceeding dma_buf after the invalidate is issued but before the copy completes they will see inconsistent data. Maybe somebody else can think of a way around that. Ryan Stone _______________________________________________ [email protected] mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-hackers To unsubscribe, send any mail to "[email protected]"
