On Thu, Nov 13, 2008 at 01:34:01AM -0800, Won De Erick wrote: > Jeremy Chadwick wrote: > > >> On Thu, Nov 13, 2008 at 12:07:37AM -0800, Won De Erick wrote: > >> Noted on this, I will update you through this thread. > >> > >> However is there any possibility of the following: > >> > >> > I don't know if there's a way to split the interrupt request for each > >> > bce's Rx and Tx, > >> > which means a total of four IRQs, and eventually four cores (or 4 CPUs) > >> > for the transactions. With this way, the IDLE processors would be > >> > utilized. > >> > >> What I mean here is, for the two interfaces: > >> > >> one IRQ for bce0 Rx > >> one IRQ for bce0 Tx > >> one IRQ for bce1 Rx > >> one IRQ for bce1 Tx > > > I can't even begin to imagine how this would be possible on any NIC. > > Yeah, but I can't also imagine how beneficial this idea when implemented.
Right -- me either. What you just said begs the question. :-) -- | Jeremy Chadwick jdc at parodius.com | | Parodius Networking http://www.parodius.com/ | | UNIX Systems Administrator Mountain View, CA, USA | | Making life hard for others since 1977. PGP: 4BD6C0CB | _______________________________________________ [email protected] mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-hardware To unsubscribe, send any mail to "[EMAIL PROTECTED]"
