Hello,
Concerning this pr:
http://www.freebsd.org/cgi/query-pr.cgi?pr=kern/124127, Given that I
have one of those 'strange' silicon here:
FreeBSD 7.1-RELEASE-p5 FreeBSD 7.1-RELEASE-p5
kernel: mskc2: <Marvell Yukon 88E8052 Gigabit Ethernet> port 0xee00-0xeeff mem
0xfdafc000-0xfdafffff irq 18 at device 0.0 on pci3
kernel: msk2: <Marvell Technology Group Ltd. Yukon EC Id 0xb6 Rev 0x02> on mskc2
kernel: msk2: Ethernet address: 00:03:2d:10:4e:26
kernel: miibus2: <MII bus> on msk2
kernel: e1000phy2: <Marvell 88E1111 Gigabit PHY> PHY 0 on miibus2
kernel: e1000phy2: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX,
1000baseTX-FDX, auto
Adding the entry: hw.msk.legacy_intr="1"to the loader.conf file solved
the problem. But applying the attached patch (written by Pyun I believe)
also solved the problem.
I think your patch should be committed for others to benefit.
Best regards,
Karim.
Index: sys/dev/msk/if_msk.c
===================================================================
--- sys/dev/msk/if_msk.c (revision 186497)
+++ sys/dev/msk/if_msk.c (working copy)
@@ -1355,27 +1355,25 @@
CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr));
/* Set the status list last index. */
CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1);
- if (sc->msk_hw_id == CHIP_ID_YUKON_EC &&
- sc->msk_hw_rev == CHIP_REV_YU_EC_A1) {
- /* WA for dev. #4.3 */
- CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
- /* WA for dev. #4.18 */
- CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21);
- CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07);
- } else {
- CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a);
- CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10);
- if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
- sc->msk_hw_rev == CHIP_REV_YU_XL_A0)
- CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04);
- else
- CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10);
- CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190);
- }
/*
- * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI.
+ * Interrupt moderation and coalescing frames should be
+ * controllable with sysctl variables or loader tunables
+ * but the relationship between status updates and
+ * interrupt moderation are not clear. Some hardware
+ * revisions seem to very sensitive to these parameters
+ * and could be resulted in poor performance as well as
+ * non-working situation if improper values were chosen.
*/
+ CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a);
+ CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10);
+ if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
+ sc->msk_hw_rev == CHIP_REV_YU_XL_A0)
+ CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04);
+ else
+ CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10);
CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000));
+ CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, MSK_USECS(sc, 30));
+ CSR_WRITE_4(sc, STAT_LEV_TIMER_INI, MSK_USECS(sc, 50));
/* Enable status unit. */
CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON);
@@ -3586,6 +3584,10 @@
domore = msk_handle_events(sc);
if ((status & Y2_IS_STAT_BMU) != 0)
CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ);
+ if (CSR_READ_1(sc, STAT_TX_TIMER_CTRL) == TIM_START) {
+ CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_STOP);
+ CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START);
+ }
if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
!IFQ_DRV_IS_EMPTY(&ifp0->if_snd))
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