Per Fogelström wrote:
On Tuesday 13 June 2006 14:23, Rick Kelly wrote:

Johnny Billquist said:

There's actually a cheesy way to do demand paging with microprocessors
that don't support demand paging (such as the original 68000--another
"16 bit" machine).  The way to do this is to run two processors in
parallel but skewed by one instruction.  If the first one does a bad
memory fetch, then the second one will not have fetched the instruction
causing the fault so contains restartable machine state.  Masscomp sold
a machine like this once.

Didn't the first Apollos do this?

And also the Sun 1.

IIRC it was simpler than that. When the first cpu caused a 'miss' it was put
in wait and cpu 2 handled the pagein and then released cpu 1. Keeping the two
cpus synched, one instruction apart would have been too complicated if not

Your idea will not work, as far as I can tell.
If the first CPU instruction execution causes a miss, the end result in the CPU will be pretty undefined, and you cannot restart. That's the whole point in why you'd have a second CPU shadowing the first one. So that you'd be able to restore the state as it were before the illegal memory access. And that was the problem with the original 68000. On an illegal memory reference, you would not know what state the CPU was in before the instruction, so you could not back it up, and re-execute the instruction after a page fault.


Johnny Billquist                  || "I'm on a bus
                                  ||  on a psychedelic trip
email: [EMAIL PROTECTED]           ||  Reading murder books
pdp is alive!                     ||  tryin' to stay hip" - B. Idol
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