Hi there,
I had the same problem about 6 months ago, and someone posted a patch that
did the trick. I have no idea who made the patch so I can't give credit.
It's attached, hope it works.
Jeff Seeman
Technical Instructor
-------------------------------------------------------------------
**** FreeBSD-Advocate ----------------------- [EMAIL PROTECTED] ****
-------------------------------------------------------------------
On Mon, 18 Nov 2002, Willy Offermans wrote:
> Dear FreeBSD friends,
>
> I have bought a nice laptop computer (Gericom Masterpiece 25340 XL).
> It has an ethernet card inside, based on SiS 900 chip.
> During boot, FreeBSD can detect the card, but cannot assign an MAC
> address, nor initializing the card. I receive following messages:
>
> ....
> sis0: <SiS 900 10/100BaseTX> port 0xf800-0xf8ff mem 0xe8005000-0xe8005fff irq 4 at
>device 4.0 on pci0
> sis0: Ethernet address: ff:ff:ff:ff:ff:ff
> sis0: MII without any PHY!
> device_probe_and_attach: sis0 attach returned 6
> ....
>
> Does anybody know to solve this problem?
>
> --
> Met vriendelijke groeten,
> With kind regards,
>
> Willy
>
> *************************************
> W.K. Offermans
> Eindhoven University of Technology
> Department of Chemical Engineering
> Laboratory of Catalysis (SKA)
> building ST-W 4.27, PO Box 513
> 5600 MB Eindhoven, Netherlands
> Tel: 0(031) 40 247 37 81
> Fax: 0(031) 40 247 50 32
> Home: 0(031) 45 544 49 99
> e-mail: [EMAIL PROTECTED]
> http://www.catalysis.nl
>
> If you are bored playing with Bill Gates' toy, start to work with a real
>operating system
> Feel free, feel FreeBSD .... (www.FreeBSD.org)
>
>
> To Unsubscribe: send mail to [EMAIL PROTECTED]
> with "unsubscribe freebsd-stable" in the body of the message
>
*** /sys/pci/if_sisreg.h Thu Feb 28 14:39:32 2002
--- if_sisreg.h Mon Jul 1 00:19:19 2002
***************
*** 124,129 ****
--- 124,151 ----
#define SIS_EECMD_READ 0x180
#define SIS_EECMD_ERASE 0x1c0
+ #define SIS_NOENPHY /* don't use Enhanced PHY Access Register */
+ #ifdef SIS_NOENPHY
+ #define SIS_MII_FRAME_START 0x4000
+ #define SIS_MII_FRAME_OP_READ 0x2000
+ #define SIS_MII_FRAME_OP_WRITE 0x1000
+ #define SIS_MII_FRAME_PMD(phy) ((phy & 0x1F) << 7)
+ #define SIS_MII_FRAME_REG(reg) ((reg & 0x1F) << 2)
+ #define SIS_MII_FRAME_LINE_READ 0x0000
+ #define SIS_MII_FRAME_LINE_WRITE 0x0002
+ #define SIS_MII_FRAME_READ(phy, reg) \
+ (SIS_MII_FRAME_START | SIS_MII_FRAME_OP_READ \
+ | SIS_MII_FRAME_PMD(phy) | SIS_MII_FRAME_REG(reg) \
+ | SIS_MII_FRAME_LINE_READ)
+ #define SIS_MII_FRAME_WRITE(phy, reg) \
+ (SIS_MII_FRAME_START | SIS_MII_FRAME_OP_WRITE \
+ | SIS_MII_FRAME_PMD(phy) | SIS_MII_FRAME_REG(reg) \
+ | SIS_MII_FRAME_LINE_WRITE)
+ #define SIS_MII_MDC 0x00000040
+ #define SIS_MII_MDDIR 0x00000020
+ #define SIS_MII_MDIO 0x00000010
+ #endif /* SIS_NOENPHY */
+
#define SIS_EE_NODEADDR 0x8
#define NS_EE_NODEADDR 0x6
*** /sys/pci/if_sis.c Thu Feb 28 14:39:32 2002
--- if_sis.c Mon Jul 1 00:11:11 2002
***************
*** 475,480 ****
--- 475,483 ----
{
struct sis_softc *sc;
int i, val = 0;
+ #ifdef SIS_NOENPHY
+ int frame_hdr = SIS_MII_FRAME_READ(phy, reg);
+ #endif
sc = device_get_softc(dev);
***************
*** 501,506 ****
--- 504,536 ----
sc->sis_rev < SIS_REV_635 && phy != 0)
return(0);
+ #ifdef SIS_NOENPHY
+ sis_eeprom_idle(sc);
+
+ for (i = (1 << 15); i; i >>= 1) {
+ int dataval = SIS_MII_MDDIR;
+ if (frame_hdr & i) {
+ dataval |= SIS_MII_MDIO;
+ }
+ CSR_WRITE_4(sc, SIS_EECTL, dataval);
+ sis_delay(sc);
+ CSR_WRITE_4(sc, SIS_EECTL, (dataval | SIS_MII_MDC));
+ sis_delay(sc);
+ }
+
+ for (i = (1 << 15); i; i >>= 1) {
+ CSR_WRITE_4(sc, SIS_EECTL, 0);
+ sis_delay(sc);
+ if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_MDIO) {
+ val |= i;
+ }
+ CSR_WRITE_4(sc, SIS_EECTL, SIS_MII_MDC);
+ sis_delay(sc);
+ }
+ CSR_WRITE_4(sc, SIS_EECTL, 0);
+
+ sis_eeprom_idle(sc);
+ #else /* SIS_NOENPHY */
CSR_WRITE_4(sc, SIS_PHYCTL, (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
***************
*** 518,523 ****
--- 548,554 ----
if (val == 0xFFFF)
return(0);
+ #endif /* SIS_NOENPHY */
return(val);
}
***************
*** 528,533 ****
--- 559,567 ----
{
struct sis_softc *sc;
int i;
+ #ifdef SIS_NOENPHY
+ int frame_hdr = SIS_MII_FRAME_WRITE(phy, reg);
+ #endif /* SIS_NOENPHY */
sc = device_get_softc(dev);
***************
*** 538,546 ****
return(0);
}
! if (sc->sis_type == SIS_TYPE_900 && phy != 0)
return(0);
CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
(reg << 6) | SIS_PHYOP_WRITE);
SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
--- 572,618 ----
return(0);
}
! if (sc->sis_type == SIS_TYPE_900 &&
! sc->sis_rev < SIS_REV_635 && phy != 0)
return(0);
+ #ifdef SIS_NOENPHY
+ sis_eeprom_idle(sc);
+
+ for (i = (1 << 15); i; i >>= 1) {
+ int dataval = SIS_MII_MDDIR;
+ if (frame_hdr & i) {
+ dataval |= SIS_MII_MDIO;
+ }
+ CSR_WRITE_4(sc, SIS_EECTL, dataval);
+ sis_delay(sc);
+ CSR_WRITE_4(sc, SIS_EECTL, (dataval | SIS_MII_MDC));
+ sis_delay(sc);
+ }
+ sis_delay(sc);
+
+ for (i = (1 << 15); i; i >>= 1) {
+ int dataval = SIS_MII_MDDIR;
+ if (data & i) {
+ dataval |= SIS_MII_MDIO;
+ }
+ CSR_WRITE_4(sc, SIS_EECTL, dataval);
+ sis_delay(sc);
+ CSR_WRITE_4(sc, SIS_EECTL, (dataval | SIS_MII_MDC));
+ sis_delay(sc);
+ }
+ sis_delay(sc);
+
+ for (i = 2; i > 0; i --) {
+ CSR_WRITE_4(sc, SIS_EECTL, 0);
+ sis_delay(sc);
+ CSR_WRITE_4(sc, SIS_EECTL, SIS_MII_MDC);
+ sis_delay(sc);
+ }
+ CSR_WRITE_4(sc, SIS_EECTL, 0);
+
+ sis_eeprom_idle(sc);
+ #else /* SIS_NOENPHY */
CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
(reg << 6) | SIS_PHYOP_WRITE);
SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
***************
*** 552,557 ****
--- 624,630 ----
if (i == SIS_TIMEOUT)
printf("sis%d: PHY failed to come ready\n", sc->sis_unit);
+ #endif /* SIS_NOENPHY */
return(0);
}
