On 2009-07-25, at 05:34, M. Warner Losh wrote:
In message: <[email protected]>
Hans Petter Selasky <[email protected]> writes:
: On Thursday 23 July 2009 20:53:06 Marcel Moolenaar wrote:
: > All,
: >
: > I went over the thread and this is what I have to say about it:
: >
: > Using busdma to manage/control CPU caches is wrong for the
: > following simple reason: bus_dmamap_sync() has the side-effect
: > of copying to and from the bounce buffer (if applicable).
: >
: > CPU caches should be kept coherent by using an appropriate API.
: > We already have cpu_flush_dcache(). All we have to do is add
: > cpu_inval_dcache() and let the MD code determine how best to
: > do this -- even if they decide to use busdma.
: >
: > In general: D-cache and I-cache control/handling should not be
: > hidden from MI code. It should not be treated as an artifact of
: > some platform. It should not be implemented by banking on some
: > side-effect of other function(s). We only achieve efficient
: > cache control if MI code calls appropriate APIs so that we can
: > precisely express what we need to achieve at that point.
: >
: > For example: when we write a breakpoint into the text segment
: > of some process by using ptrace(2), the ptrace(2) code must
: > call an appropriate API to make sure that the I-cache is made
: > coherent with memory. This may require a previous D-cache
: > flush! We should not kluge uiomove(9) like we did on PowerPC
: > to deal with this. Note ARM and ia64 are still broken in this
: > respect.
:
: Hi,
:
: I would be fine with a solution where cpufunctions are used
directly in USB.
: The only problem is that if bounce pages are used, which happens
in the case
: of loading kernel virtual data into DMA, then busdma sync calls
would still be
: required.
They are needed on i386 kernels with more than 4GB of ram... Or ram
located above 4GB...
Hans,
So how do you want to proceed with these cache sync issues? We need to
fix this before 8.0.
Rafal
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