Hi all,

I'd like to add correct bus write barriers to the ath driver.

Here's what I have thus far:


Now, it sucks that I'm doing a bus write barrier on _each_ write but
fixing it requires a lot of HAL churn and that would, well, suck.

PPC - this was a problem that was fixed by adding implicit write
flushes in your bus space. This _should_ let you get rid of that
(well, as long as you fix the rest of the drivers.)

sparc64 - if you use a PCI or PCIe ath NIC in your sparc machine,
please contact me and let me know. This should make it work (better.)

MIPS - for mips24k it's not a big problem as register accesses are in
the uncached section and are already in-order. But for mips74k and
other superscalar architectures, it will need a flush otherwise things
don't work (right.)

I'd appreciate it if this could get some testing.


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