On 12/02/2016 07:30 AM, Jordan Crouse wrote:
> Add an initial node for the Adreno GPU and it's companion
> SMMU. The GPU node is mostly complete except for a bare
> bones power table that will be filled out more completely
> later.
>
> Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
> ---

Hm.. I see that I missed the 8064 dts update and Andy has already
applied it. Sigh.

>  arch/arm64/boot/dts/qcom/msm8996.dtsi | 78 
> +++++++++++++++++++++++++++++++++++
>  1 file changed, 78 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi 
> b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index a3a4dee..4108f21 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -473,6 +473,84 @@
>                       };
>               };
>  
> +             adreno_smmu: arm,smmu@b40000 {

iommu@b40000 ?

> +                     compatible = "arm,smmu-v2";
> +                     reg = <0xb40000 0x10000>;
> +
> +                     #global-interrupts = <1>;
> +                     interrupts = <0 334 0>,
> +                                  <0 329 0>,
> +                                  <0 330 0>;

We're using the pretty macros now for GIC_SPI and irq triggers. Please
add them on interrupts.

> +                     #iommu-cells = <1>;
> +
> +                     clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>,
> +                             <&mmcc MMSS_MMAGIC_CFG_AHB_CLK>,
> +                             <&mmcc GPU_AHB_CLK>,
> +                             <&gcc GCC_MMSS_BIMC_GFX_CLK>,
> +                             <&gcc GCC_BIMC_GFX_CLK>,
> +                             <&mmcc MMSS_MISC_AHB_CLK>;
> +                     clock-names = "mmagic_ahb_clk",
> +                             "mmagic_cfg_ahb_clk",
> +                             "gpu_ahb_clk",
> +                             "gcc_mmss_bimc_gfx_clk",
> +                             "gcc_bimc_gfx_clk",
> +                             "mmss_misc_bus_clk";

Please remove _clk from all clock names as it's redundant.

> +
> +                     power-domains = <&mmcc GPU_GDSC>;
> +
> +                     qcom,skip-init;
> +                     qcom,register-save;
> +
> +                     status = "okay";

We don't need status = "okay" here. Typically those are just in the
board files.

> +             };
> +
> +             adreno-3xx@b00000 {

gpu@b00000 ?

> +                     compatible = "qcom,adreno-3xx";
> +                     #stream-id-cells = <16>;
> +
> +                     reg = <0xb00000 0x3f000>;
> +                     reg-names = "kgsl_3d0_reg_memory";
> +
> +                     interrupts = <0 300 0>;
> +                     interrupt-names = "kgsl_3d0_irq";
> +
> +                     clocks = <&mmcc GPU_GX_GFX3D_CLK>,
> +                             <&mmcc GPU_AHB_CLK>,
> +                             <&mmcc GPU_GX_RBBMTIMER_CLK>,
> +                             <&gcc GCC_BIMC_GFX_CLK>,
> +                             <&gcc GCC_MMSS_BIMC_GFX_CLK>,
> +                             <&mmcc MMSS_MMAGIC_AHB_CLK>;
> +
> +                     clock-names = "core_clk",
> +                             "iface_clk",
> +                             "rbbmtimer_clk",
> +                             "mem_clk",
> +                             "mem_iface_clk",
> +                             "alt_mem_iface_clk";

Is there a binding update for new clock names? I haven't seen it. Sad
that we couldn't remove _clk from the names here like everywhere else.

> +
> +                     power-domains = <&mmcc GPU_GDSC>;
> +                     iommus = <&adreno_smmu 0>;
> +
> +                     /* There are patchlevel 3 chips in the world (Snapdragon
> +                      * (820) but they are functionally similar to the 821 in
> +                      * the code so we can safely set the chipset as
> +                      * patchlevel 4. */
> +                     qcom,chipid = <0x05030004>;
> +
> +                     /* This is a safe speed for bring up in all bin levels.
> +                      * This isn't the fastest the chip can go, but we can
> +                      * get there eventually */
> +                     qcom,gpu-pwrlevels {
> +                             compatible = "qcom,gpu-pwrlevels";
> +                             qcom,gpu-pwrlevel@0 {
> +                                     qcom,gpu-freq = <205000000>;
> +                             };
> +                             qcom,gpu-pwrlevel@1 {
> +                                     qcom,gpu-freq = <27000000>;
> +                             };
> +                     };

These should be OPPs.

> +             };
> +
>               mdp_smmu: arm,smmu@d00000 {
>                       compatible = "arm,smmu-v2";
>                       reg = <0xd00000 0x10000>;


-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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