The amount of information that we need to pass into msm_gpu_init()
is steadily increasing, so add a new struct to stabilize the function
call and make it easier to add new configuration down the line.

Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 12 ++++++++++--
 drivers/gpu/drm/msm/msm_gpu.c           | 13 ++++++-------
 drivers/gpu/drm/msm/msm_gpu.h           | 11 ++++++++++-
 3 files changed, 26 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 247f017..53f9dea 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -344,6 +344,7 @@ int adreno_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
                struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs 
*funcs)
 {
        struct adreno_platform_config *config = pdev->dev.platform_data;
+       struct msm_gpu_config adreno_gpu_config  = { 0 };
        struct msm_gpu *gpu = &adreno_gpu->base;
        int ret;
 
@@ -364,9 +365,16 @@ int adreno_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
        DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u",
                        gpu->fast_rate, gpu->slow_rate, gpu->bus_freq);
 
+       adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
+       adreno_gpu_config.irqname = "kgsl_3d0_irq";
+
+       adreno_gpu_config.va_start = SZ_16M;
+       adreno_gpu_config.va_end = 0xffffffff;
+
+       adreno_gpu_config.ringsz = RB_SIZE;
+
        ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
-                       adreno_gpu->info->name, "kgsl_3d0_reg_memory", 
"kgsl_3d0_irq",
-                       RB_SIZE);
+                       adreno_gpu->info->name, &adreno_gpu_config);
        if (ret)
                return ret;
 
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index d336c24..bc75425 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -570,7 +570,7 @@ static irqreturn_t irq_handler(int irq, void *data)
 
 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
                struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
-               const char *name, const char *ioname, const char *irqname, int 
ringsz)
+               const char *name, struct msm_gpu_config *config)
 {
        struct iommu_domain *iommu;
        int i, ret;
@@ -606,14 +606,14 @@ int msm_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
        BUG_ON(ARRAY_SIZE(clk_names) != ARRAY_SIZE(gpu->grp_clks));
 
        /* Map registers: */
-       gpu->mmio = msm_ioremap(pdev, ioname, name);
+       gpu->mmio = msm_ioremap(pdev, config->ioname, name);
        if (IS_ERR(gpu->mmio)) {
                ret = PTR_ERR(gpu->mmio);
                goto fail;
        }
 
        /* Get Interrupt: */
-       gpu->irq = platform_get_irq_byname(pdev, irqname);
+       gpu->irq = platform_get_irq_byname(pdev, config->irqname);
        if (gpu->irq < 0) {
                ret = gpu->irq;
                dev_err(drm->dev, "failed to get irq: %d\n", ret);
@@ -657,9 +657,8 @@ int msm_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
         */
        iommu = iommu_domain_alloc(&platform_bus_type);
        if (iommu) {
-               /* TODO 32b vs 64b address space.. */
-               iommu->geometry.aperture_start = SZ_16M;
-               iommu->geometry.aperture_end = 0xffffffff;
+               iommu->geometry.aperture_start = config->va_start;
+               iommu->geometry.aperture_end = config->va_end;
 
                dev_info(drm->dev, "%s: using IOMMU\n", name);
                gpu->aspace = msm_gem_address_space_create(&pdev->dev,
@@ -678,7 +677,7 @@ int msm_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
 
        /* Create ringbuffer: */
        mutex_lock(&drm->struct_mutex);
-       gpu->rb = msm_ringbuffer_new(gpu, ringsz);
+       gpu->rb = msm_ringbuffer_new(gpu, config->ringsz);
        mutex_unlock(&drm->struct_mutex);
        if (IS_ERR(gpu->rb)) {
                ret = PTR_ERR(gpu->rb);
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index ad6d13a..cc6530f 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -28,6 +28,14 @@
 struct msm_gem_submit;
 struct msm_gpu_perfcntr;
 
+struct msm_gpu_config {
+       const char *ioname;
+       const char *irqname;
+       uint64_t va_start;
+       uint64_t va_end;
+       unsigned int ringsz;
+};
+
 /* So far, with hardware that I've seen to date, we can have:
  *  + zero, one, or two z180 2d cores
  *  + a3xx or a2xx 3d core, which share a common CP (the firmware
@@ -205,7 +213,8 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct 
msm_gem_submit *submit,
 
 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
                struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
-               const char *name, const char *ioname, const char *irqname, int 
ringsz);
+               const char *name, struct msm_gpu_config *config);
+
 void msm_gpu_cleanup(struct msm_gpu *gpu);
 
 struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
-- 
1.9.1

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