Pursuant to the arm-smmu-v3 SVM support:
I felt it would be helpful if I would demonstrate how Qualcomm implements
per-process pagetables for several generations of SoCs and GPUs focusing on the
Adreno A540 GPU and an arm-smmu-v2 IOMMU on the Snapdragon 820 SoC.
The requirement is to implement per-process GPU address spaces for security
reasons. Though some very crude SVM support is possible we focus mainly on
individual address spaces that are maintained and mapped by the GPU driver.
In a nutshell, the solution is to create special virtual or "dynamic" domains
that are associated with a real domain. The dynamic domains allocate pagetables
but do not reprogram the hardware. When a command is submitted, the kernel
driver provides the physial address of the pagetable (TTBR0) to the GPU which
reprograms the TTBR0 register in context bank 0 of the GPMU SMMU on the fly (and
does the requisite flushing and stalling).
The TTBR1 address space is used to maintain a split between the process and the
global GPU buffers (ringbuffers, etc). This greatly facilitates the switching
In more detail this is the workflow:
- The kernel driver attaches a UNMANAGED domain to context bank 0
- Global GPU buffers are allocated in the TTBR1 address space
- Each new process creates a dynamic domain cloned from the "real" domain
- New buffers for the process are mapped into the dynamic domain
- The kernel driver gets the TTBR0/ASID register value from the dynamic domain
via an attribute
- At command submission time, the kernel driver sends the TTBR0/ASID value to
the GPU before the command. The GPU switches the pagetable by programming
the SMMU hardware before executing the command.
I'll be uploading the series to implement this in the MSM DRM driver to show how
it works from the GPU perspective. I'm adding it as a separate thread to avoid
crossing the streams and confusing folks - I'll reply to this email with a link.
Obviously there are some similarities with Jean-Philippe's code and I think its
worth having the discussion about ways we can merge the concepts on that thread.
There are a few barriers to overcome but in general I think we can find a way
Please review if you want and provide comment or just follow along.
Jeremy Gebben (2):
iommu: introduce TTBR0 domain attribute
iommu/arm-smmu: add support for TTBR0 attribute
Jordan Crouse (4):
iommu: Add DOMAIN_ATTR_ENABLE_TTBR1
iommu/arm-smmu: Add support for TTBR1
iommu: Add dynamic domains
iommu/arm-smmu: add support for dynamic domains
Mitchel Humpherys (1):
iommu/arm-smmu: save the pgtbl_cfg in the domain
drivers/iommu/arm-smmu.c | 198 +++++++++++++++++++++++++++++++++++------
drivers/iommu/io-pgtable-arm.c | 168 ++++++++++++++++++++++++++++++----
drivers/iommu/io-pgtable.h | 6 ++
drivers/iommu/iommu.c | 37 ++++++++
include/linux/iommu.h | 19 +++-
5 files changed, 382 insertions(+), 46 deletions(-)
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