A5XX GPUs can be run in either 32 or 64 bit mode. The GPU registers
and the microcode use 64 bit virtual addressing in either case but the
upper 32 bits are ignored if the GPU is in 32 bit mode. There is no
performance disadvantage to remaining in 64 bit mode even if we are
only generating 32 bit addresses so switch over now to prepare for
using addresses above 4G for targets that support them.

Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 14 ++++++++++++++
 drivers/gpu/drm/msm/msm_iommu.c       |  7 +++----
 2 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index fef1541..06238b7 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -800,6 +800,20 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
                REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000);
        gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);
 
+       /* Put the GPU into 64 bit by default */
+       gpu_write(gpu, REG_A5XX_CP_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A5XX_VSC_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A5XX_GRAS_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A5XX_RB_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A5XX_PC_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A5XX_HLSQ_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A5XX_VFD_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A5XX_VPC_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A5XX_UCHE_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A5XX_SP_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A5XX_TPL1_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
+
        /* Load the GPMU firmware before starting the HW init */
        a5xx_gpmu_ucode_init(gpu);
 
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index 7521582..d520db2 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/gpu/drm/msm/msm_iommu.c
@@ -34,10 +34,9 @@ static int msm_fault_handler(struct iommu_domain *domain, 
struct device *dev,
        if (iommu->base.handler)
                ret = iommu->base.handler(iommu->base.arg, iova, flags);
        else
-               pr_warn_ratelimited("*** fault: iova=%08lx, flags=%d\n", iova, 
flags);
+               pr_warn_ratelimited("*** fault: iova=%16lx, flags=%d\n", iova, 
flags);
 
        iommu_domain_resume(domain, false);
-
        return 0;
 }
 
@@ -104,7 +103,7 @@ static int msm_iommu_map(struct msm_mmu *mmu, uint64_t iova,
                dma_addr_t pa = sg_phys(sg) - sg->offset;
                size_t bytes = sg->length + sg->offset;
 
-               VERB("map[%d]: %08lx %08lx(%zx)", i, da, (unsigned long)pa, 
bytes);
+               VERB("map[%d]: %16lx %16lx(%zx)", i, da, (unsigned long)pa, 
bytes);
 
                ret = iommu_map(domain, da, pa, bytes, prot);
                if (ret)
@@ -143,7 +142,7 @@ static int msm_iommu_unmap(struct msm_mmu *mmu, uint64_t 
iova,
                if (unmapped < bytes)
                        return unmapped;
 
-               VERB("unmap[%d]: %08lx(%zx)", i, da, bytes);
+               VERB("unmap[%d]: %16lx(%zx)", i, da, bytes);
 
                BUG_ON(!PAGE_ALIGNED(bytes));
 
-- 
1.9.1

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