Even though the default countable for CP0 is CP_ALWAYS_COUNT (0),
program the selector during HW initialization in an effort to be
up front about which counters are programmed and why.

Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index fdbe9e9..56c2c44 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -597,6 +597,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
        /* Turn on performance counters */
        gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_CNTL, 0x01);
 
+       /* Select CP0 to always count cycles */
+       gpu_write(gpu, REG_A5XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);
+
        /* Increase VFD cache access so LRZ and other data gets evicted less */
        gpu_write(gpu, REG_A5XX_UCHE_CACHE_WAYS, 0x02);
 
-- 
1.9.1

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