On Mon, Apr 16, 2018 at 11:22:16AM -0700, Jeykumar Sankaran wrote:
> Upstream DSI driver doesn't support DSC panels yet. Remove
> the support for compression from DPU for now.
>
> Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
> ---
> drivers/gpu/drm/msm/Makefile | 1 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c | 4 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 476
> +--------------------
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 14 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 7 +-
> .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 1 -
> .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 7 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 25 --
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 16 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 252 -----------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 100 -----
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 17 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 48 ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 22 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 13 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 7 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 55 ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 8 -
> drivers/gpu/drm/msm/msm_drv.h | 16 -
> 20 files changed, 7 insertions(+), 1084 deletions(-)
> delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
> delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
>
> diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
> index 9c27991..b23a001 100644
> --- a/drivers/gpu/drm/msm/Makefile
> +++ b/drivers/gpu/drm/msm/Makefile
> @@ -64,7 +64,6 @@ msm-y := \
> disp/dpu1/dpu_hw_color_processing_v1_7.o \
> disp/dpu1/dpu_hw_ctl.o \
> disp/dpu1/dpu_hw_ds.o \
> - disp/dpu1/dpu_hw_dsc.o \
> disp/dpu1/dpu_hw_dspp.o \
> disp/dpu1/dpu_hw_interrupts.o \
> disp/dpu1/dpu_hw_intf.o \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
> index 36607e3..1237efc 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
> @@ -39,12 +39,8 @@
> static const struct drm_prop_enum_list e_topology_name[] = {
> {DPU_RM_TOPOLOGY_NONE, "dpu_none"},
> {DPU_RM_TOPOLOGY_SINGLEPIPE, "dpu_singlepipe"},
> - {DPU_RM_TOPOLOGY_SINGLEPIPE_DSC, "dpu_singlepipe_dsc"},
> {DPU_RM_TOPOLOGY_DUALPIPE, "dpu_dualpipe"},
> - {DPU_RM_TOPOLOGY_DUALPIPE_DSC, "dpu_dualpipe_dsc"},
> {DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE, "dpu_dualpipemerge"},
> - {DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC, "dpu_dualpipemerge_dsc"},
> - {DPU_RM_TOPOLOGY_DUALPIPE_DSCMERGE, "dpu_dualpipe_dscmerge"},
> {DPU_RM_TOPOLOGY_PPSPLIT, "dpu_ppsplit"},
> };
> static const struct drm_prop_enum_list e_topology_control[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> index 8756b2b..fade658 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> @@ -147,7 +147,7 @@ struct dpu_crtc_event {
> * @num_ctls : Number of ctl paths in use
> * @num_mixers : Number of mixers in use
> * @mixers_swapped: Whether the mixers have been swapped for left/right
> update
> - * especially in the case of DSC Merge.
> + especially in the case of DSC Merge.
> * @mixers : List of active mixers
> * @event : Pointer to last received drm vblank event. If there is a
> * pending vblank event, this will be non-null.
Unrelated change
<snip />
> static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt
> *dpu_enc,
> struct msm_display_info *disp_info)
> {
> @@ -1109,102 +761,8 @@ static void _dpu_encoder_update_vsync_source(struct
> dpu_encoder_virt *dpu_enc,
>
> hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
> }
> -}
> -
> -static int _dpu_encoder_dsc_disable(struct dpu_encoder_virt *dpu_enc)
> -{
> - enum dpu_rm_topology_name topology;
> - struct drm_connector *drm_conn;
> - int i, ret = 0;
> - struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
> - struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC] = {NULL};
> - int pp_count = 0;
> - int dsc_count = 0;
> -
> - if (!dpu_enc || !dpu_enc->phys_encs[0] ||
> - !dpu_enc->phys_encs[0]->connector) {
> - DPU_ERROR("invalid params %d %d\n",
> - !dpu_enc, dpu_enc ? !dpu_enc->phys_encs[0] : -1);
> - return -EINVAL;
> - }
> -
> - drm_conn = dpu_enc->phys_encs[0]->connector;
> -
> - topology = dpu_connector_get_topology_name(drm_conn);
> - if (topology == DPU_RM_TOPOLOGY_NONE) {
> - DPU_ERROR_ENC(dpu_enc, "topology not set yet\n");
> - return -EINVAL;
> - }
> -
> - switch (topology) {
> - case DPU_RM_TOPOLOGY_SINGLEPIPE:
> - case DPU_RM_TOPOLOGY_SINGLEPIPE_DSC:
> - /* single PP */
> - hw_pp[0] = dpu_enc->hw_pp[0];
> - hw_dsc[0] = dpu_enc->hw_dsc[0];
> - pp_count = 1;
> - dsc_count = 1;
> - break;
> - case DPU_RM_TOPOLOGY_DUALPIPE_DSC:
> - case DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC:
> - case DPU_RM_TOPOLOGY_DUALPIPE_DSCMERGE:
> - /* dual dsc */
> - for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
> - hw_dsc[i] = dpu_enc->hw_dsc[i];
> - if (hw_dsc[i])
> - dsc_count++;
> - }
> - /* fall through */
> - case DPU_RM_TOPOLOGY_DUALPIPE:
> - case DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE:
> - /* dual pp */
> - for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
> - hw_pp[i] = dpu_enc->hw_pp[i];
> - if (hw_pp[i])
> - pp_count++;
> - }
> - break;
> - default:
> - DPU_DEBUG_ENC(dpu_enc, "Unexpected topology:%d\n", topology);
> - return -EINVAL;
> - };
> -
> - DPU_EVT32(DRMID(&dpu_enc->base), topology, pp_count, dsc_count);
> -
> - if (pp_count > MAX_CHANNELS_PER_ENC ||
> - dsc_count > MAX_CHANNELS_PER_ENC) {
> - DPU_ERROR_ENC(dpu_enc, "Wrong count pp:%d dsc:%d top:%d\n",
> - pp_count, dsc_count, topology);
> - return -EINVAL;
> - }
> -
> - /* Disable DSC for all the pp's present in this topology */
> - for (i = 0; i < pp_count; i++) {
> -
> - if (!hw_pp[i]) {
> - DPU_ERROR_ENC(dpu_enc, "null pp:%d top:%d cnt:%d\n",
> - i, topology, pp_count);
> - return -EINVAL;
> - }
> -
> - if (hw_pp[i]->ops.disable_dsc)
> - hw_pp[i]->ops.disable_dsc(hw_pp[i]);
> - }
> -
> - /* Disable DSC HW */
> - for (i = 0; i < dsc_count; i++) {
> -
> - if (!hw_dsc[i]) {
> - DPU_ERROR_ENC(dpu_enc, "null dsc:%d top:%d cnt:%d\n",
> - i, topology, dsc_count);
> - return -EINVAL;
> - }
> -
> - if (hw_dsc[i]->ops.dsc_disable)
> - hw_dsc[i]->ops.dsc_disable(hw_dsc[i]);
> - }
>
> - return ret;
> + return;
Unnecessary return
<snip />
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> @@ -232,7 +232,6 @@ struct dpu_encoder_irq {
> * @split_role: Role to play in a split-panel configuration
> * @intf_mode: Interface mode
> * @intf_idx: Interface index on dpu hardware
> - * @comp_type: Type of compression supported
> * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
> * @enable_state: Enable state tracking
> * @vblank_refcount: Reference count of vblank request
> @@ -262,7 +261,6 @@ struct dpu_encoder_phys {
> enum dpu_enc_split_role split_role;
> enum dpu_intf_mode intf_mode;
> enum dpu_intf intf_idx;
> - enum msm_display_compression_type comp_type;
> spinlock_t *enc_spinlock;
> enum dpu_enc_enable_state enable_state;
> atomic_t vblank_refcount;
> @@ -384,7 +382,6 @@ struct dpu_encoder_phys_wb {
> * @split_role: Role to play in a split-panel configuration
> * @intf_idx: Interface index this phys_enc will control
> * @wb_idx: Writeback index this phys_enc will control
> - * @comp_type: Type of compression supported
> * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
> */
> struct dpu_enc_phys_init_params {
> @@ -394,7 +391,6 @@ struct dpu_enc_phys_init_params {
> enum dpu_enc_split_role split_role;
> enum dpu_intf intf_idx;
> enum dpu_wb wb_idx;
> - enum msm_display_compression_type comp_type;
> spinlock_t *enc_spinlock;
> };
>
> @@ -479,8 +475,7 @@ static inline enum dpu_3d_blend_mode
> dpu_encoder_helper_get_3d_blend_mode(
>
> topology = dpu_connector_get_topology_name(phys_enc->connector);
> if (phys_enc->split_role == ENC_ROLE_SOLO &&
> - (topology == DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE ||
> - topology == DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC))
> + topology == DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE)
nit: the alignment is still off, it should line up with the previous condition,
ie:
if (phys_enc->split_role == ENC_ROLE_SOLO &&
topology == DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE)
> return BLEND_3D_H_ROW_INT;
>
> return BLEND_3D_NONE;
<snip />
Once the nits are fixed, please add my
Reviewed-by: Sean Paul <seanp...@chromium.org>
Thanks,
Sean
>
> --
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--
Sean Paul, Software Engineer, Google / Chromium OS
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