Now that we don't have arbitrary register dumping, remove the macro and
just call dpu_dbg_dump directly.
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
drivers/gpu/drm/msm/dpu_dbg.c | 37 +++++--------------
drivers/gpu/drm/msm/dpu_dbg.h | 23 ++++--------
5 files changed, 21 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 3519f7e84f0f..ce4faee12adc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1563,7 +1563,7 @@ void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys
*phys_enc)
rc = ctl->ops.reset(ctl);
if (rc) {
DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx);
- DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus");
+ dpu_dbg_dump(false, __func__, true, true);
}
phys_enc->enable_state = DPU_ENC_ENABLED;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 19f5b5064ed8..9519dbc24266 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -262,7 +262,7 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
atomic_read(&phys_enc->pending_kickoff_cnt));
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR);
- DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus");
+ dpu_dbg_dump(false, __func__, true, true);
}
atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 54f4e78cf1fd..110c463077ed 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -638,7 +638,7 @@ static void dpu_encoder_phys_vid_prepare_for_kickoff(
DPU_ERROR_VIDENC(vid_enc, "ctl %d reset failure: %d\n",
ctl->idx, rc);
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC);
- DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus");
+ dpu_dbg_dump(false, __func__, true, true);
}
}
diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/dpu_dbg.c
index 51d46975cc27..ae2aee7ed9e1 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.c
+++ b/drivers/gpu/drm/msm/dpu_dbg.c
@@ -2248,39 +2248,22 @@ static void _dpu_dump_work(struct work_struct *work)
dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work);
}
-void dpu_dbg_dump(bool queue_work, const char *name, ...)
+void dpu_dbg_dump(bool queue_work, const char *name, bool dump_dbgbus_dpu,
+ bool dump_dbgbus_vbif_rt)
{
- bool dump_dbgbus_dpu = false;
- bool dump_dbgbus_vbif_rt = false;
- va_list args;
- char *blk_name = NULL;
-
if (queue_work && work_pending(&dpu_dbg_base.dump_work))
return;
- va_start(args, name);
- while ((blk_name = va_arg(args, char*))) {
- if (IS_ERR_OR_NULL(blk_name))
- break;
-
- if (!strcmp(blk_name, "dbg_bus"))
- dump_dbgbus_dpu = true;
-
- if (!strcmp(blk_name, "vbif_dbg_bus"))
- dump_dbgbus_vbif_rt = true;
- }
- va_end(args);
-
- if (queue_work) {
- /* schedule work to dump later */
- dpu_dbg_base.dbgbus_dpu.cmn.include_in_deferred_work =
- dump_dbgbus_dpu;
- dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work =
- dump_dbgbus_vbif_rt;
- schedule_work(&dpu_dbg_base.dump_work);
- } else {
+ if (!queue_work) {
_dpu_dump_array(name, dump_dbgbus_dpu, dump_dbgbus_vbif_rt);
+ return;
}
+
+ /* schedule work to dump later */
+ dpu_dbg_base.dbgbus_dpu.cmn.include_in_deferred_work = dump_dbgbus_dpu;
+ dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work =
+ dump_dbgbus_vbif_rt;
+ schedule_work(&dpu_dbg_base.dump_work);
}
/*
diff --git a/drivers/gpu/drm/msm/dpu_dbg.h b/drivers/gpu/drm/msm/dpu_dbg.h
index 6a247ce39997..05504e676f6a 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.h
+++ b/drivers/gpu/drm/msm/dpu_dbg.h
@@ -22,14 +22,6 @@ enum dpu_dbg_dump_flag {
DPU_DBG_DUMP_IN_MEM = BIT(1),
};
-/**
- * DPU_DBG_DUMP - trigger dumping of all dpu_dbg facilities
- * @va_args: list of named register dump ranges and regions to dump, as
- * registered previously through dpu_dbg_reg_register_base and
- * dpu_dbg_reg_register_dump_range.
- */
-#define DPU_DBG_DUMP(...) dpu_dbg_dump(false, __func__, ##__VA_ARGS__, NULL)
-
#if defined(CONFIG_DEBUG_FS)
/**
@@ -60,14 +52,14 @@ void dpu_dbg_destroy(void);
/**
* dpu_dbg_dump - trigger dumping of all dpu_dbg facilities
- * @queue_work: whether to queue the dumping work to the work_struct
- * @name: string indicating origin of dump
- * @va_args: list of named register dump ranges and regions to dump, as
- * registered previously through dpu_dbg_reg_register_base and
- * dpu_dbg_reg_register_dump_range.
+ * @queue_work: whether to queue the dumping work to the work_struct
+ * @name: string indicating origin of dump
+ * @dump_dbgbus: dump the dpu debug bus
+ * @dump_vbif_rt: dump the vbif rt bus
* Returns: none
*/
-void dpu_dbg_dump(bool queue_work, const char *name, ...);
+void dpu_dbg_dump(bool queue_work, const char *name, bool dump_dbgbus_dpu,
+ bool dump_dbgbus_vbif_rt);
/**
* dpu_dbg_set_dpu_top_offset - set the target specific offset from mdss base
@@ -105,7 +97,8 @@ static inline void dpu_dbg_destroy(void)
{
}
-static inline void dpu_dbg_dump(bool queue_work, const char *name, ...)
+static inline void dpu_dbg_dump(bool queue_work, const char *name,
+ bool dump_dbgbus_dpu, bool dump_dbgbus_vbif_rt);
{
}
--
Sean Paul, Software Engineer, Google / Chromium OS
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