On Wed, Feb 13, 2019 at 05:19:11PM -0800, Jeykumar Sankaran wrote:
> Not holding any video encoder specific data. Get rid of it.
>
> Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
Reviewed-by: Sean Paul <s...@poorly.run>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 11 -----------
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 18 ++++--------------
> 2 files changed, 4 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> index acd5956..9b1efd9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> @@ -254,17 +254,6 @@ static inline int dpu_encoder_phys_inc_pending(struct
> dpu_encoder_phys *phys)
> }
>
> /**
> - * struct dpu_encoder_phys_vid - sub-class of dpu_encoder_phys to handle
> video
> - * mode specific operations
> - * @base: Baseclass physical encoder structure
> - * @timing_params: Current timing parameter
> - */
> -struct dpu_encoder_phys_vid {
> - struct dpu_encoder_phys base;
> - struct intf_timing_params timing_params;
> -};
> -
> -/**
> * struct dpu_encoder_phys_cmd - sub-class of dpu_encoder_phys to handle
> command
> * mode specific operations
> * @base: Baseclass physical encoder structure
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index e326395..ce65521 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -240,7 +240,6 @@ static bool dpu_encoder_phys_vid_mode_fixup(
> static void dpu_encoder_phys_vid_setup_timing_engine(
> struct dpu_encoder_phys *phys_enc)
> {
> - struct dpu_encoder_phys_vid *vid_enc;
> struct drm_display_mode mode;
> struct intf_timing_params timing_params = { 0 };
> const struct dpu_format *fmt = NULL;
> @@ -254,7 +253,6 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
> }
>
> mode = phys_enc->cached_mode;
> - vid_enc = to_dpu_encoder_phys_vid(phys_enc);
> if (!phys_enc->hw_intf->ops.setup_timing_gen) {
> DPU_ERROR("timing engine setup is not supported\n");
> return;
> @@ -293,8 +291,6 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
> spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
>
> programmable_fetch_config(phys_enc, &timing_params);
> -
> - vid_enc->timing_params = timing_params;
> }
>
> static void dpu_encoder_phys_vid_vblank_irq(void *arg, int irq_idx)
> @@ -515,16 +511,13 @@ static void dpu_encoder_phys_vid_enable(struct
> dpu_encoder_phys *phys_enc)
>
> static void dpu_encoder_phys_vid_destroy(struct dpu_encoder_phys *phys_enc)
> {
> - struct dpu_encoder_phys_vid *vid_enc;
> -
> if (!phys_enc) {
> DPU_ERROR("invalid encoder\n");
> return;
> }
>
> - vid_enc = to_dpu_encoder_phys_vid(phys_enc);
> DPU_DEBUG_VIDENC(phys_enc, "\n");
> - kfree(vid_enc);
> + kfree(phys_enc);
> }
>
> static void dpu_encoder_phys_vid_get_hw_resources(
> @@ -747,7 +740,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
> struct dpu_enc_phys_init_params *p)
> {
> struct dpu_encoder_phys *phys_enc = NULL;
> - struct dpu_encoder_phys_vid *vid_enc = NULL;
> struct dpu_encoder_irq *irq;
> int i, ret = 0;
>
> @@ -756,14 +748,12 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
> goto fail;
> }
>
> - vid_enc = kzalloc(sizeof(*vid_enc), GFP_KERNEL);
> - if (!vid_enc) {
> + phys_enc = kzalloc(sizeof(*phys_enc), GFP_KERNEL);
> + if (!phys_enc) {
> ret = -ENOMEM;
> goto fail;
> }
>
> - phys_enc = &vid_enc->base;
> -
> phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
> phys_enc->intf_idx = p->intf_idx;
>
> @@ -807,7 +797,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
>
> fail:
> DPU_ERROR("failed to create encoder\n");
> - if (vid_enc)
> + if (phys_enc)
> dpu_encoder_phys_vid_destroy(phys_enc);
>
> return ERR_PTR(ret);
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
> _______________________________________________
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--
Sean Paul, Software Engineer, Google / Chromium OS
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