On Thu, Sep 26, 2019 at 12:52:52PM +0200, khol...@gmail.com wrote:
> From: "Angelo G. Del Regno" <khol...@gmail.com>
Hi Angelo,
Thank you for your patches!
>
> Some SoCs, like MSM8956/8976 (and APQ variants), do feature these
> clocks and we need to enable them in order to get the hardware to
> properly work.
Could you add an explanation to the commit message of what these
clocks are/do, for those of us who don't know?
>
> Signed-off-by: Angelo G. Del Regno <khol...@gmail.com>
> ---
> Documentation/devicetree/bindings/display/msm/mdp5.txt | 2 ++
> drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 10 ++++++++++
> drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h | 2 ++
> 3 files changed, 14 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/mdp5.txt
> b/Documentation/devicetree/bindings/display/msm/mdp5.txt
> index 4e11338548aa..43d11279c925 100644
> --- a/Documentation/devicetree/bindings/display/msm/mdp5.txt
> +++ b/Documentation/devicetree/bindings/display/msm/mdp5.txt
> @@ -76,6 +76,8 @@ Required properties:
> Optional properties:
> - clock-names: the following clocks are optional:
> * "lut"
> + * "tbu"
> + * "tbu_rt"
Bindings updates should be in their own patch, and you'll need to cc the correct
dt lists and maintainers (especially Rob Herring) in order to get their
attention. (hint: use scripts/get_maintainer.pl)
Sean
>
> Example:
>
> diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
> b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
> index fec6ef1ae3b9..23be9b95dd7e 100644
> --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
> +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
> @@ -293,6 +293,10 @@ int mdp5_disable(struct mdp5_kms *mdp5_kms)
> mdp5_kms->enable_count--;
> WARN_ON(mdp5_kms->enable_count < 0);
>
> + if (mdp5_kms->tbu_rt_clk)
> + clk_disable_unprepare(mdp5_kms->tbu_rt_clk);
> + if (mdp5_kms->tbu_clk)
> + clk_disable_unprepare(mdp5_kms->tbu_clk);
> clk_disable_unprepare(mdp5_kms->ahb_clk);
> clk_disable_unprepare(mdp5_kms->axi_clk);
> clk_disable_unprepare(mdp5_kms->core_clk);
> @@ -313,6 +317,10 @@ int mdp5_enable(struct mdp5_kms *mdp5_kms)
> clk_prepare_enable(mdp5_kms->core_clk);
> if (mdp5_kms->lut_clk)
> clk_prepare_enable(mdp5_kms->lut_clk);
> + if (mdp5_kms->tbu_clk)
> + clk_prepare_enable(mdp5_kms->tbu_clk);
> + if (mdp5_kms->tbu_rt_clk)
> + clk_prepare_enable(mdp5_kms->tbu_rt_clk);
>
> return 0;
> }
> @@ -948,6 +956,8 @@ static int mdp5_init(struct platform_device *pdev, struct
> drm_device *dev)
>
> /* optional clocks: */
> get_clk(pdev, &mdp5_kms->lut_clk, "lut", false);
> + get_clk(pdev, &mdp5_kms->tbu_clk, "tbu", false);
> + get_clk(pdev, &mdp5_kms->tbu_rt_clk, "tbu_rt", false);
>
> /* we need to set a default rate before enabling. Set a safe
> * rate first, then figure out hw revision, and then set a
> diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
> b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
> index d1bf4fdfc815..128866742593 100644
> --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
> +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
> @@ -53,6 +53,8 @@ struct mdp5_kms {
> struct clk *ahb_clk;
> struct clk *core_clk;
> struct clk *lut_clk;
> + struct clk *tbu_clk;
> + struct clk *tbu_rt_clk;
> struct clk *vsync_clk;
>
> /*
> --
> 2.21.0
>
--
Sean Paul, Software Engineer, Google / Chromium OS
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