Attempt to enable split pagetables if the arm-smmu driver supports it.
This will move the default address space from the default region to
the address range assigned to TTBR1. The behavior should be transparent
to the driver for now but it gets the default buffers out of the way
when we want to start swapping TTBR0 for context-specific pagetables.

Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---

 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 46 ++++++++++++++++++++++++++++++++++-
 1 file changed, 45 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 5dc0b2c..96b3b28 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -811,6 +811,50 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu)
        return (unsigned long)busy_time;
 }
 
+static struct msm_gem_address_space *
+a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)
+{
+       struct iommu_domain *iommu = iommu_domain_alloc(&platform_bus_type);
+       struct msm_gem_address_space *aspace;
+       struct msm_mmu *mmu;
+       u64 start, size;
+       u32 val = 1;
+       int ret;
+
+       if (!iommu)
+               return ERR_PTR(-ENOMEM);
+
+       /* Try to request split pagetables */
+       iommu_domain_set_attr(iommu, DOMAIN_ATTR_SPLIT_TABLES, &val);
+
+       mmu = msm_iommu_new(&pdev->dev, iommu);
+       if (IS_ERR(mmu)) {
+               iommu_domain_free(iommu);
+               return ERR_CAST(mmu);
+       }
+
+       /* Check to see if split pagetables were successful */
+       ret = iommu_domain_get_attr(iommu, DOMAIN_ATTR_SPLIT_TABLES, &val);
+       if (!ret && val) {
+               /*
+                * The aperture start will be at the beginning of the TTBR1
+                * space so use that as a base
+                */
+               start = iommu->geometry.aperture_start;
+               size = 0xffffffff;
+       } else {
+               /* Otherwise use the legacy 32 bit region */
+               start = SZ_16M;
+               size = 0xffffffff - SZ_16M;
+       }
+
+       aspace = msm_gem_address_space_create(mmu, "gpu", start, size);
+       if (IS_ERR(aspace))
+               iommu_domain_free(iommu);
+
+       return aspace;
+}
+
 static const struct adreno_gpu_funcs funcs = {
        .base = {
                .get_param = adreno_get_param,
@@ -832,7 +876,7 @@ static const struct adreno_gpu_funcs funcs = {
 #if defined(CONFIG_DRM_MSM_GPU_STATE)
                .gpu_state_get = a6xx_gpu_state_get,
                .gpu_state_put = a6xx_gpu_state_put,
-               .create_address_space = adreno_iommu_create_address_space,
+               .create_address_space = a6xx_create_address_space,
 #endif
        },
        .get_timestamp = a6xx_get_timestamp,
-- 
2.7.4

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