Fix max core clk rate during dt parsing in display driver.

Signed-off-by: Shubhashree Dhar <d...@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c
index 27fbeb5..991fff1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c
@@ -187,6 +187,7 @@ int msm_dss_parse_clock(struct platform_device *pdev,
                        continue;
                mp->clk_config[i].rate = rate;
                mp->clk_config[i].type = DSS_CLK_PCLK;
+               mp->clk_config[i].max_rate = rate;
        }
 
        mp->num_clk = num_clk;
-- 
1.9.1

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