dpu: define interrupt register names

abhinavk Mon, 24 May 2021 14:51:21 -0700

On 2021-05-16 13:29, Dmitry Baryshkov wrote:

In order to make mdss_irqs readable (and error-prone) define names for

I think you meant "less error-prone" here.

interrupt register indices.


Signed-off-by: Dmitry Baryshkov <[email protected]>

With that nit fixed,
Reviewed-by: Abhinav Kumar <[email protected]>

---
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c    | 45 ++++++++++++++++---
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 18 ++++++++
 2 files changed, 58 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index b569030a0847..9a77d64d3fd4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -7,6 +7,7 @@
 #include <linux/of_address.h>
 #include <linux/platform_device.h>
 #include "dpu_hw_mdss.h"
+#include "dpu_hw_interrupts.h"
 #include "dpu_hw_catalog.h"
 #include "dpu_kms.h"

@@ -56,6 +57,23 @@

 #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)

+#define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+                        BIT(MDP_SSPP_TOP0_INTR2) | \
+                        BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+                        BIT(MDP_INTF0_INTR) | \
+                        BIT(MDP_INTF1_INTR) | \
+                        BIT(MDP_INTF2_INTR) | \
+                        BIT(MDP_INTF3_INTR) | \
+                        BIT(MDP_INTF4_INTR) | \
+                        BIT(MDP_AD4_0_INTR) | \
+                        BIT(MDP_AD4_1_INTR))
+
+#define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+                        BIT(MDP_SSPP_TOP0_INTR2) | \
+                        BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+                        BIT(MDP_INTF0_INTR) | \
+                        BIT(MDP_INTF1_INTR))
+
 #define INTR_SC7180_MASK \
        (BIT(DPU_IRQ_TYPE_PING_PONG_RD_PTR) |\
        BIT(DPU_IRQ_TYPE_PING_PONG_WR_PTR) |\
@@ -63,6 +81,23 @@
        BIT(DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK) |\
        BIT(DPU_IRQ_TYPE_PING_PONG_TE_CHECK))

+#define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+                        BIT(MDP_SSPP_TOP0_INTR2) | \
+                        BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+                        BIT(MDP_INTF0_7xxx_INTR) | \
+                        BIT(MDP_INTF1_7xxx_INTR) | \
+                        BIT(MDP_INTF5_7xxx_INTR))
+
+#define IRQ_SM8250_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+                        BIT(MDP_SSPP_TOP0_INTR2) | \
+                        BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+                        BIT(MDP_INTF0_INTR) | \
+                        BIT(MDP_INTF1_INTR) | \
+                        BIT(MDP_INTF2_INTR) | \
+                        BIT(MDP_INTF3_INTR) | \
+                        BIT(MDP_INTF4_INTR))
+
+
 #define DEFAULT_PIXEL_RAM_SIZE         (50 * 1024)
 #define DEFAULT_DPU_LINE_WIDTH         2048
 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH  2560

@@ -1060,7 +1095,7 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg*dpu_cfg)

                .reg_dma_count = 1,
                .dma_cfg = sdm845_regdma,
                .perf = sdm845_perf_data,
-               .mdss_irqs = 0x3ff,
+               .mdss_irqs = IRQ_SDM845_MASK,
        };
 }

@@ -1091,7 +1126,7 @@ static void sc7180_cfg_init(struct dpu_mdss_cfg*dpu_cfg)

                .reg_dma_count = 1,
                .dma_cfg = sdm845_regdma,
                .perf = sc7180_perf_data,
-               .mdss_irqs = 0x3f,
+               .mdss_irqs = IRQ_SC7180_MASK,
                .obsolete_irq = INTR_SC7180_MASK,
        };
 }

@@ -1125,7 +1160,7 @@ static void sm8150_cfg_init(struct dpu_mdss_cfg*dpu_cfg)

                .reg_dma_count = 1,
                .dma_cfg = sm8150_regdma,
                .perf = sm8150_perf_data,
-               .mdss_irqs = 0x3ff,
+               .mdss_irqs = IRQ_SDM845_MASK,
        };
 }

@@ -1158,7 +1193,7 @@ static void sm8250_cfg_init(struct dpu_mdss_cfg*dpu_cfg)

                .reg_dma_count = 1,
                .dma_cfg = sm8250_regdma,
                .perf = sm8250_perf_data,
-               .mdss_irqs = 0xff,
+               .mdss_irqs = IRQ_SM8250_MASK,
        };
 }

@@ -1181,7 +1216,7 @@ static void sc7280_cfg_init(struct dpu_mdss_cfg*dpu_cfg)

                .vbif_count = ARRAY_SIZE(sdm845_vbif),
                .vbif = sdm845_vbif,
                .perf = sc7280_perf_data,
-               .mdss_irqs = 0x1c07,
+               .mdss_irqs = IRQ_SC7280_MASK,
                .obsolete_irq = INTR_SC7180_MASK,
        };
 }
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index 5bade5637ecc..b26a3445a8eb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -74,6 +74,24 @@ enum dpu_intr_type {
        DPU_IRQ_TYPE_RESERVED,
 };

+/* When making changes be sure to sync with dpu_intr_set */
+enum dpu_hw_intr_reg {
+       MDP_SSPP_TOP0_INTR,
+       MDP_SSPP_TOP0_INTR2,
+       MDP_SSPP_TOP0_HIST_INTR,
+       MDP_INTF0_INTR,
+       MDP_INTF1_INTR,
+       MDP_INTF2_INTR,
+       MDP_INTF3_INTR,
+       MDP_INTF4_INTR,
+       MDP_AD4_0_INTR,
+       MDP_AD4_1_INTR,
+       MDP_INTF0_7xxx_INTR,
+       MDP_INTF1_7xxx_INTR,
+       MDP_INTF5_7xxx_INTR,
+       MDP_INTR_MAX,
+};
+
 struct dpu_hw_intr;

 /**

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Re: [Freedreno] [PATCH v2 3/6] drm/msm/dpu: define interrupt register names

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