On 12.02.2023 00:12, Dmitry Baryshkov wrote:
> Signed-off-by: Dmitry Baryshkov <[email protected]>
> ---
> .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 96 +++++++++++++++++++
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 90 +----------------
> 2 files changed, 98 insertions(+), 88 deletions(-)
> create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> new file mode 100644
> index 000000000000..aadb65329ec3
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> @@ -0,0 +1,96 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DPU_6_3_SM6115_H
> +#define _DPU_6_3_SM6115_H
> +
> +static const struct dpu_caps sm6115_dpu_caps = {
> + .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
> + .max_mixer_blendstages = 0x4,
> + .qseed_type = DPU_SSPP_SCALER_QSEED4,
> + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
Rebase
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> + .has_dim_layer = true,
> + .has_idle_pc = true,
> + .max_linewidth = 2160,
> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +};
> +
> +static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = {
> + .ubwc_version = DPU_HW_UBWC_VER_10,
> + .highest_bank_bit = 0x1,
> + .ubwc_swizzle = 0x7,
> +};
> +
> +static const struct dpu_mdp_cfg sm6115_mdp[] = {
> + {
> + .name = "top_0", .id = MDP_TOP,
> + .base = 0x0, .len = 0x494,
> + .features = 0,
> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> + },
> +};
> +
> +static const struct dpu_sspp_cfg sm6115_sspp[] = {
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> + sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> +};
> +
> +static const struct dpu_perf_cfg sm6115_perf_data = {
> + .max_bw_low = 3100000,
> + .max_bw_high = 4000000,
> + .min_core_ib = 2400000,
> + .min_llcc_ib = 800000,
> + .min_dram_ib = 800000,
> + .min_prefill_lines = 24,
> + .danger_lut_tbl = {0xff, 0xffff, 0x0},
> + .safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
> + .qos_lut_tbl = {
> + {.nentry = ARRAY_SIZE(sc7180_qos_linear),
> + .entries = sc7180_qos_linear
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
> + .entries = sc7180_qos_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> + .entries = sc7180_qos_nrt
> + },
> + /* TODO: macrotile-qseed is different from macrotile */
> + },
> + .cdp_cfg = {
> + {.rd_enable = 1, .wr_enable = 1},
> + {.rd_enable = 1, .wr_enable = 0}
> + },
> + .clk_inefficiency_factor = 105,
> + .bw_inefficiency_factor = 120,
> +};
> +
> +static const struct dpu_mdss_cfg sm6115_dpu_cfg = {
> + .caps = &sm6115_dpu_caps,
> + .ubwc = &sm6115_ubwc_cfg,
> + .mdp_count = ARRAY_SIZE(sm6115_mdp),
> + .mdp = sm6115_mdp,
> + .ctl_count = ARRAY_SIZE(qcm2290_ctl),
> + .ctl = qcm2290_ctl,
> + .sspp_count = ARRAY_SIZE(sm6115_sspp),
> + .sspp = sm6115_sspp,
> + .mixer_count = ARRAY_SIZE(qcm2290_lm),
> + .mixer = qcm2290_lm,
> + .dspp_count = ARRAY_SIZE(qcm2290_dspp),
> + .dspp = qcm2290_dspp,
> + .pingpong_count = ARRAY_SIZE(qcm2290_pp),
> + .pingpong = qcm2290_pp,
> + .intf_count = ARRAY_SIZE(qcm2290_intf),
> + .intf = qcm2290_intf,
> + .vbif_count = ARRAY_SIZE(sdm845_vbif),
> + .vbif = sdm845_vbif,
> + .perf = &sm6115_perf_data,
> + .mdss_irqs = IRQ_SC7180_MASK,
> +};
> +
> +#endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index f7a940fe67ff..15ac2a86dbb1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -349,17 +349,6 @@ static const struct dpu_caps sc7180_dpu_caps = {
> .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> };
>
> -static const struct dpu_caps sm6115_dpu_caps = {
> - .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
> - .max_mixer_blendstages = 0x4,
> - .qseed_type = DPU_SSPP_SCALER_QSEED4,
> - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
> - .has_dim_layer = true,
> - .has_idle_pc = true,
> - .max_linewidth = 2160,
> - .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> -};
> -
> static const struct dpu_caps sm8150_dpu_caps = {
> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> .max_mixer_blendstages = 0xb,
> @@ -422,12 +411,6 @@ static const struct dpu_ubwc_cfg sc7180_ubwc_cfg = {
> .highest_bank_bit = 0x3,
> };
>
> -static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = {
> - .ubwc_version = DPU_HW_UBWC_VER_10,
> - .highest_bank_bit = 0x1,
> - .ubwc_swizzle = 0x7,
> -};
> -
> static const struct dpu_ubwc_cfg sm8150_ubwc_cfg = {
> .ubwc_version = DPU_HW_UBWC_VER_30,
> .highest_bank_bit = 0x2,
> @@ -538,18 +521,6 @@ static const struct dpu_mdp_cfg sc8180x_mdp[] = {
> },
> };
>
> -static const struct dpu_mdp_cfg sm6115_mdp[] = {
> - {
> - .name = "top_0", .id = MDP_TOP,
> - .base = 0x0, .len = 0x494,
> - .features = 0,
> - .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> - .reg_off = 0x2ac, .bit_off = 0},
> - .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
> - .reg_off = 0x2ac, .bit_off = 8},
> - },
> -};
> -
> static const struct dpu_mdp_cfg sm8250_mdp[] = {
> {
> .name = "top_0", .id = MDP_TOP,
> @@ -885,13 +856,6 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
> static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =
> _VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED4);
>
> -static const struct dpu_sspp_cfg sm6115_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> - sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> -};
> -
> static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
> _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4);
> static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
> @@ -1666,35 +1630,6 @@ static const struct dpu_perf_cfg sc7180_perf_data = {
> .bw_inefficiency_factor = 120,
> };
>
> -static const struct dpu_perf_cfg sm6115_perf_data = {
> - .max_bw_low = 3100000,
> - .max_bw_high = 4000000,
> - .min_core_ib = 2400000,
> - .min_llcc_ib = 800000,
> - .min_dram_ib = 800000,
> - .min_prefill_lines = 24,
> - .danger_lut_tbl = {0xff, 0xffff, 0x0},
> - .safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
> - .qos_lut_tbl = {
> - {.nentry = ARRAY_SIZE(sc7180_qos_linear),
> - .entries = sc7180_qos_linear
> - },
> - {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
> - .entries = sc7180_qos_macrotile
> - },
> - {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> - .entries = sc7180_qos_nrt
> - },
> - /* TODO: macrotile-qseed is different from macrotile */
> - },
> - .cdp_cfg = {
> - {.rd_enable = 1, .wr_enable = 1},
> - {.rd_enable = 1, .wr_enable = 0}
> - },
> - .clk_inefficiency_factor = 105,
> - .bw_inefficiency_factor = 120,
> -};
> -
> static const struct dpu_perf_cfg sm8150_perf_data = {
> .max_bw_low = 12800000,
> .max_bw_high = 12800000,
> @@ -1881,29 +1816,6 @@ static const struct dpu_mdss_cfg sc7180_dpu_cfg = {
> .mdss_irqs = IRQ_SC7180_MASK,
> };
>
> -static const struct dpu_mdss_cfg sm6115_dpu_cfg = {
> - .caps = &sm6115_dpu_caps,
> - .ubwc = &sm6115_ubwc_cfg,
> - .mdp_count = ARRAY_SIZE(sm6115_mdp),
> - .mdp = sm6115_mdp,
> - .ctl_count = ARRAY_SIZE(qcm2290_ctl),
> - .ctl = qcm2290_ctl,
> - .sspp_count = ARRAY_SIZE(sm6115_sspp),
> - .sspp = sm6115_sspp,
> - .mixer_count = ARRAY_SIZE(qcm2290_lm),
> - .mixer = qcm2290_lm,
> - .dspp_count = ARRAY_SIZE(qcm2290_dspp),
> - .dspp = qcm2290_dspp,
> - .pingpong_count = ARRAY_SIZE(qcm2290_pp),
> - .pingpong = qcm2290_pp,
> - .intf_count = ARRAY_SIZE(qcm2290_intf),
> - .intf = qcm2290_intf,
> - .vbif_count = ARRAY_SIZE(sdm845_vbif),
> - .vbif = sdm845_vbif,
> - .perf = &sm6115_perf_data,
> - .mdss_irqs = IRQ_SC7180_MASK,
> -};
> -
> static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
> .caps = &sm8150_dpu_caps,
> .ubwc = &sm8150_ubwc_cfg,
> @@ -2012,6 +1924,8 @@ static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
> .mdss_irqs = IRQ_SC7180_MASK,
> };
>
> +#include "catalog/dpu_6_3_sm6115.h"
> +
> #include "catalog/dpu_7_0_sm8350.h"
> #include "catalog/dpu_7_2_sc7280.h"
>
