The "vsync_hz" variable is unsigned int so it can't be less than zero. The dpu_kms_get_clk_rate() function used to return a u64 but I previously changed it to return an unsigned long and zero on error so it matches clk_get_rate().
Change the "vsync_hz" type to unsigned long as well and change the error checking to check for zero instead of negatives. This change does not affect runtime at all beyond a minor adjustment to the debug output. Suggested-by: Marijn Suijten <[email protected]> Signed-off-by: Dan Carpenter <[email protected]> Reviewed-by: Marijn Suijten <[email protected]> --- v2: update the debug output drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 4f8c9187f76d..27a823c72c06 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -323,8 +323,8 @@ static void dpu_encoder_phys_cmd_tearcheck_config( to_dpu_encoder_phys_cmd(phys_enc); struct dpu_hw_tear_check tc_cfg = { 0 }; struct drm_display_mode *mode; + unsigned long vsync_hz; bool tc_enable = true; - u32 vsync_hz; struct dpu_kms *dpu_kms; if (phys_enc->has_intf_te) { @@ -359,9 +359,8 @@ static void dpu_encoder_phys_cmd_tearcheck_config( * frequency divided by the no. of rows (lines) in the LCDpanel. */ vsync_hz = dpu_kms_get_clk_rate(dpu_kms, "vsync"); - if (vsync_hz <= 0) { - DPU_DEBUG_CMDENC(cmd_enc, "invalid - vsync_hz %u\n", - vsync_hz); + if (!vsync_hz) { + DPU_DEBUG_CMDENC(cmd_enc, "no vsync clock\n"); return; } @@ -381,7 +380,7 @@ static void dpu_encoder_phys_cmd_tearcheck_config( tc_cfg.rd_ptr_irq = mode->vdisplay + 1; DPU_DEBUG_CMDENC(cmd_enc, - "tc vsync_clk_speed_hz %u vtotal %u vrefresh %u\n", + "tc vsync_clk_speed_hz %lu vtotal %u vrefresh %u\n", vsync_hz, mode->vtotal, drm_mode_vrefresh(mode)); DPU_DEBUG_CMDENC(cmd_enc, "tc enable %u start_pos %u rd_ptr_irq %u\n", -- 2.39.2
