Re: [Freedreno] [PATCH 11/15] drm/msm/dsi: Add 14nm phy configuration for SM6125

[Dmitry Baryshkov]

On 24/06/2023 04:49, Konrad Dybcio wrote:

On 24.06.2023 02:41, Marijn Suijten wrote:

SM6125 features only a single PHY (despite a secondary PHY PLL source
being available to the disp_cc_mdss_pclk0_clk_src clock), and downstream
sources for this "trinket" SoC do not define the typical "vcca"
regulator to be available nor used.

Signed-off-by: Marijn Suijten <marijn.suij...@somainline.org>
---

The introduced ops are identical to 2290, modulo regulator..

But the regulator is absent on both (VDD_MX powers it instead), so
feel free to clean that up and reuse it ;)

Could you please send a fix for qcm2290?

Konrad

  drivers/gpu/drm/msm/dsi/phy/dsi_phy.c      |  2 ++
  drivers/gpu/drm/msm/dsi/phy/dsi_phy.h      |  1 +
  drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 15 +++++++++++++++
  3 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 9d5795c58a98..8688ed502dcf 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -559,6 +559,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
          .data = &dsi_phy_14nm_2290_cfgs },
        { .compatible = "qcom,dsi-phy-14nm-660",
          .data = &dsi_phy_14nm_660_cfgs },
+       { .compatible = "qcom,dsi-phy-14nm-6125",
+         .data = &dsi_phy_14nm_6125_cfgs },
        { .compatible = "qcom,dsi-phy-14nm-8953",
          .data = &dsi_phy_14nm_8953_cfgs },
  #endif
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 8b640d174785..ebf915f5e6c6 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -52,6 +52,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
  extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
  extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
  extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_14nm_6125_cfgs;
  extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs;
  extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
  extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 3ce45b023e63..5d43c9ec69ae 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -1068,6 +1068,21 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
        .num_dsi_phy = 2,
  };

+const struct msm_dsi_phy_cfg dsi_phy_14nm_6125_cfgs = {

+       .has_phy_lane = true,
+       .ops = {
+               .enable = dsi_14nm_phy_enable,
+               .disable = dsi_14nm_phy_disable,
+               .pll_init = dsi_pll_14nm_init,
+               .save_pll_state = dsi_14nm_pll_save_state,
+               .restore_pll_state = dsi_14nm_pll_restore_state,
+       },
+       .min_pll_rate = VCO_MIN_RATE,
+       .max_pll_rate = VCO_MAX_RATE,
+       .io_start = { 0x5e94400 },
+       .num_dsi_phy = 1,
+};
+
  const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = {
        .has_phy_lane = true,
        .regulator_data = dsi_phy_14nm_17mA_regulators,

--
With best wishes
Dmitry