[PATCH] drm/msm/dpu: fix vblank IRQ handling for command panels

[Dmitry Baryshkov]

In case of CMD DSI panels, the vblank IRQ can be used outside of
irq_enable/irq_disable pair. This results in the following kind of
messages. Move assignment of IRQ indices to atomic_enable /
atomic_disable callbacks.

[dpu error]invalid IRQ=[134217727, 31]
[drm:dpu_encoder_phys_cmd_control_vblank_irq] *ERROR* vblank irq err id:31 pp:0 
ret:-22, enable true/0
[drm:dpu_encoder_phys_cmd_control_vblank_irq] *ERROR* vblank irq err id:31 pp:0 
ret:-22, enable false/0

Fixes: d13f638c9b88 ("drm/msm/dpu: drop dpu_encoder_phys_ops.atomic_mode_set")
Signed-off-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org>
---
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   | 24 +++++++++++-----------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index fc1d5736d7fc..2a2b607bd1ab 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -280,14 +280,6 @@ static void dpu_encoder_phys_cmd_irq_enable(struct 
dpu_encoder_phys *phys_enc)
                                          phys_enc->hw_pp->idx - PINGPONG_0,
                                          phys_enc->vblank_refcount);
 
-       phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start;
-       phys_enc->irq[INTR_IDX_PINGPONG] = phys_enc->hw_pp->caps->intr_done;
-
-       if (phys_enc->has_intf_te)
-               phys_enc->irq[INTR_IDX_RDPTR] = 
phys_enc->hw_intf->cap->intr_tear_rd_ptr;
-       else
-               phys_enc->irq[INTR_IDX_RDPTR] = 
phys_enc->hw_pp->caps->intr_rdptr;
-
        dpu_core_irq_register_callback(phys_enc->dpu_kms,
                                       phys_enc->irq[INTR_IDX_PINGPONG],
                                       dpu_encoder_phys_cmd_pp_tx_done_irq,
@@ -318,10 +310,6 @@ static void dpu_encoder_phys_cmd_irq_disable(struct 
dpu_encoder_phys *phys_enc)
        dpu_core_irq_unregister_callback(phys_enc->dpu_kms, 
phys_enc->irq[INTR_IDX_UNDERRUN]);
        dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, false);
        dpu_core_irq_unregister_callback(phys_enc->dpu_kms, 
phys_enc->irq[INTR_IDX_PINGPONG]);
-
-       phys_enc->irq[INTR_IDX_CTL_START] = 0;
-       phys_enc->irq[INTR_IDX_PINGPONG] = 0;
-       phys_enc->irq[INTR_IDX_RDPTR] = 0;
 }
 
 static void dpu_encoder_phys_cmd_tearcheck_config(
@@ -472,6 +460,14 @@ static void dpu_encoder_phys_cmd_enable(struct 
dpu_encoder_phys *phys_enc)
                return;
        }
 
+       phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start;
+       phys_enc->irq[INTR_IDX_PINGPONG] = phys_enc->hw_pp->caps->intr_done;
+
+       if (phys_enc->has_intf_te)
+               phys_enc->irq[INTR_IDX_RDPTR] = 
phys_enc->hw_intf->cap->intr_tear_rd_ptr;
+       else
+               phys_enc->irq[INTR_IDX_RDPTR] = 
phys_enc->hw_pp->caps->intr_rdptr;
+
        dpu_encoder_phys_cmd_enable_helper(phys_enc);
        phys_enc->enable_state = DPU_ENC_ENABLED;
 }
@@ -563,6 +559,10 @@ static void dpu_encoder_phys_cmd_disable(struct 
dpu_encoder_phys *phys_enc)
                ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);
        }
 
+       phys_enc->irq[INTR_IDX_CTL_START] = 0;
+       phys_enc->irq[INTR_IDX_PINGPONG] = 0;
+       phys_enc->irq[INTR_IDX_RDPTR] = 0;
+
        phys_enc->enable_state = DPU_ENC_DISABLED;
 }
 

---
base-commit: 13ee4a7161b6fd938aef6688ff43b163f6d83e37
change-id: 20240330-dpu-fix-irqs-56eb08fcb9d4

Best regards,
-- 
Dmitry Baryshkov <dmitry.barysh...@linaro.org>