On Fri, 5 Apr 2024 at 02:43, Stephen Boyd <[email protected]> wrote: > > Commit ec17373aebd0 ("phy: qcom: qmp-combo: extract common function to > setup clocks") changed the offset that is used to write to > DP_PHY_VCO_DIV from QSERDES_V3_DP_PHY_VCO_DIV to > QSERDES_V4_DP_PHY_VCO_DIV. Unfortunately, this offset is different > between v3 and v4 phys: > > #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 > #define QSERDES_V4_DP_PHY_VCO_DIV 0x070 > > meaning that we write the wrong register on v3 phys now. Add another > generic register to 'regs' and use it here instead of a version specific > define to fix this. > > This was discovered after Abhinav looked over register dumps with me > from sc7180 Trogdor devices that started failing to light up the > external display with v6.6 based kernels. It turns out that some > monitors are very specific about their link clk frequency and if the > default power on reset value is still there the monitor will show a > blank screen or a garbled display. Other monitors are perfectly happy to > get a bad clock signal. > > Cc: Douglas Anderson <[email protected]> > Cc: Abhinav Kumar <[email protected]> > Cc: Dmitry Baryshkov <[email protected]> > Fixes: ec17373aebd0 ("phy: qcom: qmp-combo: extract common function to setup > clocks") > Signed-off-by: Stephen Boyd <[email protected]> > --- > drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-)
Reviewed-by: Dmitry Baryshkov <[email protected]> -- With best wishes Dmitry
