On 31/01/2025 17:25, Dmitry Baryshkov wrote:
>>
>> -static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll)
>> +static void dsi_pll_cmn_clk_cfg1_update(struct dsi_pll_7nm *pll, u32 mask,
>> + u32 val)
>> {
>> + unsigned long flags;
>> u32 data;
>>
>> + spin_lock_irqsave(&pll->pclk_mux_lock, flags);
>> data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
>> - writel(data & ~BIT(5), pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
>> + data &= ~mask;
>> + data |= val & mask;
>> +
>> + writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
>> + spin_unlock_irqrestore(&pll->pclk_mux_lock, flags);
>> +}
>> +
>> +static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll)
>> +{
>> + dsi_pll_cmn_clk_cfg1_update(pll, BIT(5), 0);
>
> PLease add these bits to the corresponding XML file (here and later on)
I need some more input from you - I don't know which XML you talk about.
Do you think about:
drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
and others alike? But doesn't it have only register offsets, not field
offsets?
Best regards,
Krzysztof
