From: Akhil P Oommen <[email protected]> [ Upstream commit 0c5300343d0c622f7852145a763c570fbaf68a48 ]
Add speedbin mappings for A663 GPU. Signed-off-by: Akhil P Oommen <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/670096/ Signed-off-by: Rob Clark <[email protected]> Signed-off-by: Sasha Levin <[email protected]> --- LLM Generated explanations, may be completely bogus: YES Why this should be backported - Fixes incorrect OPP selection for A663: The change adds `.speedbins` for the A663 entry so the driver can translate hardware fuse values to the correct speed-bin bit used for OPP filtering. Without this mapping, the driver logs “missing support for speed-bin” and falls back to bin 0, which can lead to selecting the wrong OPPs or even no OPPs for some boards. New mapping added at drivers/gpu/drm/msm/adreno/a6xx_catalog.c:1032: - drivers/gpu/drm/msm/adreno/a6xx_catalog.c:1032 - drivers/gpu/drm/msm/adreno/a6xx_catalog.c:1033 - drivers/gpu/drm/msm/adreno/a6xx_catalog.c:1034 - drivers/gpu/drm/msm/adreno/a6xx_catalog.c:1035 - Directly addresses the code path that depends on speedbins: `a6xx_set_supported_hw()` reads the fuse via `adreno_read_speedbin()`, maps it with `fuse_to_supp_hw()`, and programs the mask via `devm_pm_opp_set_supported_hw()`. If the mapping is missing, it warns and defaults to `BIT(0)`, potentially mismatching the board’s OPP table: - Mapping lookup: drivers/gpu/drm/msm/adreno/a6xx_gpu.c:2483 - Missing mapping fallback and OPP mask set: drivers/gpu/drm/msm/adreno/a6xx_gpu.c:2516, drivers/gpu/drm/msm/adreno/a6xx_gpu.c:2523 - Minimal, data-only change: No architectural changes; it only adds a speedbin table for one GPU ID. The macro and field already exist and are used elsewhere: - Speedbin field docs: drivers/gpu/drm/msm/adreno/adreno_gpu.h:111 - Speedbin helper macro: drivers/gpu/drm/msm/adreno/adreno_gpu.h:148 - User impact: On A663 devices where the fuse reads 113 (now mapped to speedbin 1), the previous default to bin 0 could underclock the GPU or make the OPP table unusable if the DT only defines bin-1 OPPs. This change ensures correct and safe OPP filtering for real hardware configurations. - Stable criteria fit: Important functional fix for existing hardware; small, isolated change; no new features; low regression risk; limited to the msm/adreno driver. Risk and scope - Scope: Only the A663 GPU entry is touched, mapping fuses `{0,0}`, `{169,0}`, `{113,1}`. Devices with fuse 169 see no behavioral change versus fallback; devices with fuse 113 now correctly use bin 1 instead of incorrectly defaulting to bin 0. - Regression risk: Very low. The OPP filter machinery and speedbin infrastructure are already in place. This commit simply supplies the missing mapping data for one GPU variant. drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 00e1afd46b815..2b1c41f6cfeee 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1024,6 +1024,11 @@ static const struct adreno_info a6xx_gpus[] = { .gmu_cgc_mode = 0x00020200, .prim_fifo_threshold = 0x00300200, }, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 169, 0 }, + { 113, 1 }, + ), }, { .chip_ids = ADRENO_CHIP_IDS(0x06030500), .family = ADRENO_6XX_GEN4, -- 2.51.0
