From: Akhil P Oommen <[email protected]> [ Upstream commit 0584da4515dbb4fec69107ce837eef36a7be5d7d ]
Add the speedbin mappings for Adreno 623 GPU. Signed-off-by: Akhil P Oommen <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/672462/ Signed-off-by: Rob Clark <[email protected]> Signed-off-by: Sasha Levin <[email protected]> --- LLM Generated explanations, may be completely bogus: YES Rationale - What changed: Adds speedbin-to-bin mappings for Adreno 623 so the driver can correctly gate OPPs based on fuse value: - A623 entry: drivers/gpu/drm/msm/adreno/a6xx_catalog.c:889 - New mapping: drivers/gpu/drm/msm/adreno/a6xx_catalog.c:916 - { 0, 0 }, { 185, 0 }, { 127, 1 } - Why it matters: The a6xx driver reads the GPU’s speed-bin fuse and filters usable OPPs accordingly. Without a mapping, the code falls back to BIT(0), which can enable OPPs meant only for faster bins on slower-binned parts (risking instability or rendering faults): - Fuse read: drivers/gpu/drm/msm/adreno/adreno_gpu.c:1173 - Mapping lookup and fallback: - fuse_to_supp_hw() uses info->speedbins: drivers/gpu/drm/msm/adreno/a6xx_gpu.c:2485 - If no mapping, logs error and defaults to BIT(0): drivers/gpu/drm/msm/adreno/a6xx_gpu.c:2514, drivers/gpu/drm/msm/adreno/a6xx_gpu.c:2520 - Device-tree evidence (A623-class SoC) shows higher OPPs are explicitly restricted to bin 0, making correct speedbin mapping essential: - NVMEM speed_bin: arch/arm64/boot/dts/qcom/qcs8300.dtsi:4316 - OPP table: arch/arm64/boot/dts/qcom/qcs8300.dtsi:4324 - Top OPPs only for BIT(0): arch/arm64/boot/dts/qcom/qcs8300.dtsi:4331, arch/arm64/boot/dts/qcom/qcs8300.dtsi:4338 - Lower OPPs for BIT(0)|BIT(1): arch/arm64/boot/dts/qcom/qcs8300.dtsi:4345, arch/arm64/boot/dts/qcom/qcs8300.dtsi:4352 - Without this patch, slower-binned A623 parts would be misidentified as bin 0 and incorrectly allowed to use these top OPPs. - Stable backport fit: - Bug fix: Correctly enforces hardware-supported OPPs based on fuses for A623, preventing potential over-frequency/undervoltage conditions on slower bins. - Small and contained: Adds a data table entry; no API or architectural change. - Low regression risk: Aligns A623 with how other a6xx GPUs already use speedbins; expected outcome is correct OPP gating (performance might decrease on mis-binned systems, but that is the intended fix). - Touches a single DRM/msm driver file; no core kernel impact. - No new features; strictly correctness and reliability for existing hardware support. Conclusion - This is a clear, low-risk correctness fix for A623 platforms and should be backported to stable trees that include A623 support. drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 2b1c41f6cfeee..3c82b3f320e3a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -913,6 +913,11 @@ static const struct adreno_info a6xx_gpus[] = { { /* sentinel */ }, }, }, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 185, 0 }, + { 127, 1 }, + ), }, { .chip_ids = ADRENO_CHIP_IDS( 0x06030001, -- 2.51.0
