On the latest A8xx Adreno chips several of the bits in the UBWC-related registers are now hardwired to 1. Currently the driver doesn't write them because there is no side-effect. In the preparation for the refactoring in the next patch, write '1' to those bits anyway.
Signed-off-by: Dmitry Baryshkov <[email protected]> --- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index 53def136e0fc..7a6223ddd8cf 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -288,6 +288,8 @@ static void a8xx_set_ubwc_config(struct msm_gpu *gpu) switch (ubwc_version) { case UBWC_6_0: yuvnotcomptofc = true; + amsbc = true; + rgb565_predicator = true; break; case UBWC_5_0: amsbc = true; -- 2.47.3
