On 5/7/2026 6:33 PM, Dmitry Baryshkov wrote: > From: Konrad Dybcio <[email protected]> > > Now that the highest_bank_bit value is retrieved from the running > system and the global config has been part of the tree for a couple > of releases, there is no reason to keep any hardcoded values inside > the GPU driver. > > Get rid of them. > > Signed-off-by: Konrad Dybcio <[email protected]> > Reviewed-by: Rob Clark <[email protected]> > Reviewed-by: Dmitry Baryshkov <[email protected]> > Signed-off-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Akhil P Oommen <[email protected]> -Akhil. > --- > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 11 ++--- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 82 > ++------------------------------- > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 -- > 3 files changed, 6 insertions(+), 92 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > index 79acae11154a..699fc0f551ed 100644 > --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > @@ -1725,7 +1725,6 @@ static struct msm_gpu *a5xx_gpu_init(struct drm_device > *dev) > struct msm_drm_private *priv = dev->dev_private; > struct platform_device *pdev = priv->gpu_pdev; > struct adreno_platform_config *config = pdev->dev.platform_data; > - const struct qcom_ubwc_cfg_data *common_cfg; > struct a5xx_gpu *a5xx_gpu = NULL; > struct adreno_gpu *adreno_gpu; > struct msm_gpu *gpu; > @@ -1769,13 +1768,9 @@ static struct msm_gpu *a5xx_gpu_init(struct drm_device > *dev) > a5xx_preempt_init(gpu); > > /* Inherit the common config and make some necessary fixups */ > - common_cfg = qcom_ubwc_config_get_data(); > - if (IS_ERR(common_cfg)) > - return ERR_CAST(common_cfg); > - > - /* Copy the data into the internal struct to drop the const qualifier > (temporarily) */ > - adreno_gpu->_ubwc_config = *common_cfg; > - adreno_gpu->ubwc_config = &adreno_gpu->_ubwc_config; > + adreno_gpu->ubwc_config = qcom_ubwc_config_get_data(); > + if (IS_ERR(adreno_gpu->ubwc_config)) > + return ERR_CAST(adreno_gpu->ubwc_config); > > adreno_gpu->uche_trap_base = 0x0001ffffffff0000ull; > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index d5aba072f44c..1d998636c5a3 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -733,82 +733,6 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) > gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), > protect->regs[i]); > } > > -static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) > -{ > - const struct qcom_ubwc_cfg_data *common_cfg; > - struct qcom_ubwc_cfg_data *cfg = &gpu->_ubwc_config; > - > - /* Inherit the common config and make some necessary fixups */ > - common_cfg = qcom_ubwc_config_get_data(); > - if (IS_ERR(common_cfg)) > - return PTR_ERR(common_cfg); > - > - /* Copy the data into the internal struct to drop the const qualifier > (temporarily) */ > - *cfg = *common_cfg; > - > - /* Use common config as is for A8x */ > - if (!adreno_is_a8xx(gpu)) { > - cfg->ubwc_swizzle = 0x6; > - cfg->highest_bank_bit = 15; > - } > - > - if (adreno_is_a610(gpu)) { > - cfg->highest_bank_bit = 13; > - cfg->ubwc_swizzle = 0x7; > - } > - > - if (adreno_is_a612(gpu)) > - cfg->highest_bank_bit = 14; > - > - if (adreno_is_a618(gpu)) > - cfg->highest_bank_bit = 14; > - > - if (adreno_is_a619(gpu)) > - /* TODO: Should be 14 but causes corruption at e.g. 1920x1200 > on DP */ > - cfg->highest_bank_bit = 13; > - > - if (adreno_is_a619_holi(gpu)) > - cfg->highest_bank_bit = 13; > - > - if (adreno_is_a621(gpu)) > - cfg->highest_bank_bit = 13; > - > - if (adreno_is_a623(gpu)) > - cfg->highest_bank_bit = 16; > - > - if (adreno_is_a650(gpu) || > - adreno_is_a660(gpu) || > - adreno_is_a690(gpu) || > - adreno_is_a730(gpu) || > - adreno_is_a740_family(gpu)) { > - /* TODO: get ddr type from bootloader and use 15 for LPDDR4 */ > - cfg->highest_bank_bit = 16; > - } > - > - if (adreno_is_a663(gpu)) { > - cfg->highest_bank_bit = 13; > - cfg->ubwc_swizzle = 0x4; > - } > - > - if (adreno_is_7c3(gpu)) > - cfg->highest_bank_bit = 14; > - > - if (adreno_is_a702(gpu)) > - cfg->highest_bank_bit = 14; > - > - if (cfg->highest_bank_bit != common_cfg->highest_bank_bit) > - DRM_WARN_ONCE("Inconclusive highest_bank_bit value: %u (GPU) vs > %u (UBWC_CFG)\n", > - cfg->highest_bank_bit, > common_cfg->highest_bank_bit); > - > - if (cfg->ubwc_swizzle != common_cfg->ubwc_swizzle) > - DRM_WARN_ONCE("Inconclusive ubwc_swizzle value: %u (GPU) vs %u > (UBWC_CFG)\n", > - cfg->ubwc_swizzle, common_cfg->ubwc_swizzle); > - > - gpu->ubwc_config = &gpu->_ubwc_config; > - > - return 0; > -} > - > static void a6xx_set_ubwc_config(struct msm_gpu *gpu) > { > struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > @@ -2701,10 +2625,10 @@ static struct msm_gpu *a6xx_gpu_init(struct > drm_device *dev) > msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu, > adreno_gpu->funcs->mmu_fault_handler); > > - ret = a6xx_calc_ubwc_config(adreno_gpu); > - if (ret) { > + adreno_gpu->ubwc_config = qcom_ubwc_config_get_data(); > + if (IS_ERR(adreno_gpu->ubwc_config)) { > a6xx_destroy(&(a6xx_gpu->base.base)); > - return ERR_PTR(ret); > + return ERR_CAST(adreno_gpu->ubwc_config); > } > > /* Set up the preemption specific bits and pieces for each ringbuffer */ > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > index ec643b84646b..324319762383 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > @@ -236,12 +236,7 @@ struct adreno_gpu { > /* firmware: */ > const struct firmware *fw[ADRENO_FW_MAX]; > > - /* > - * The migration to the central UBWC config db is still in flight - keep > - * a copy containing some local fixups until that's done. > - */ > const struct qcom_ubwc_cfg_data *ubwc_config; > - struct qcom_ubwc_cfg_data _ubwc_config; > > /* > * Register offsets are different between some GPUs. >
