Re: [PATCH RESEND v5 02/25] drm/msm/dp: introduce max_streams for DP controller MST support

[Yongxing Mou]

On 7/12/2026 7:17 PM, Dmitry Baryshkov wrote:

On Mon, Jun 29, 2026 at 10:14:23PM +0800, Yongxing Mou wrote:

From: Abhinav Kumar <quic_abhin...@quicinc.com>

DP controllers across different SoCs vary in the number of concurrent
MST streams they can support. Rather than hardcoding per-platform
values, the number of available pixel clocks in DT serves as a natural
indicator since each stream requires a dedicated pixel clock.

Introduce max_stream to capture this at initialization time and expose
it for the MST module to use during setup.

Signed-off-by: Abhinav Kumar <quic_abhin...@quicinc.com>
Signed-off-by: Yongxing Mou <yongxing....@oss.qualcomm.com>
---
  drivers/gpu/drm/msm/dp/dp_ctrl.c    | 13 +++++++++++++
  drivers/gpu/drm/msm/dp/dp_ctrl.h    |  1 +
  drivers/gpu/drm/msm/dp/dp_display.c | 12 ++++++++++++
  drivers/gpu/drm/msm/dp/dp_display.h |  1 +
  4 files changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index a475e787656e..68fb4facb056 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -127,6 +127,7 @@ struct msm_dp_ctrl_private {
        struct clk_bulk_data *link_clks;

struct clk *pixel_clk[DP_STREAM_MAX];

+       unsigned int num_pixel_clks;

Squash num_pixel_clks to the previous patch.

Got it.

union phy_configure_opts phy_opts; @@ -2754,6 +2755,7 @@ static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl)

        if (rc)
                return rc;

+ ctrl->num_pixel_clks = 0;

        for (i = DP_STREAM_0; i < DP_STREAM_MAX; i++) {
                ctrl->pixel_clk[i] = devm_clk_get(dev, pixel_clks[i]);

@@ -2766,11 +2768,22 @@ static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl)

                        DRM_DEBUG_DP("stream %d pixel clock not found", i);
                        break;
                }
+
+               ctrl->num_pixel_clks++;
        }

return 0;

  }

+int msm_dp_ctrl_get_stream_cnt(struct msm_dp_ctrl *msm_dp_ctrl)

+{
+       struct msm_dp_ctrl_private *ctrl;
+
+       ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, 
msm_dp_ctrl);
+
+       return ctrl->num_pixel_clks;
+}
+
  struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link 
*link,
                        struct drm_dp_aux *aux,
                        struct phy *phy,
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h
index be0d89d60914..305add3dcd93 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.h
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h
@@ -55,4 +55,5 @@ void msm_dp_ctrl_enable_irq(struct msm_dp_ctrl *msm_dp_ctrl);
  void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl);

void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl);

+int msm_dp_ctrl_get_stream_cnt(struct msm_dp_ctrl *dp_ctrl);
  #endif /* _DP_CTRL_H_ */
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c 
b/drivers/gpu/drm/msm/dp/dp_display.c
index bb243ab09e66..9cd243411e44 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -87,6 +87,8 @@ struct msm_dp_display_private {

void __iomem *p0_base;

        size_t p0_len;
+
+       int max_stream;
  };

struct msm_dp_desc {

@@ -578,6 +580,7 @@ static int msm_dp_init_sub_modules(struct 
msm_dp_display_private *dp)
                dp->ctrl = NULL;
                goto error_link;
        }
+       dp->max_stream = msm_dp_ctrl_get_stream_cnt(dp->ctrl);

dp->audio = msm_dp_audio_get(dp->msm_dp_display.pdev, dp->link_base);

        if (IS_ERR(dp->audio)) {
@@ -1178,6 +1181,15 @@ static int msm_dp_display_get_io(struct 
msm_dp_display_private *display)
        return 0;
  }

+int msm_dp_get_mst_max_stream(struct msm_dp *msm_dp_display)

+{
+       struct msm_dp_display_private *dp;
+
+       dp = container_of(msm_dp_display, struct msm_dp_display_private, 
msm_dp_display);
+
+       return dp->max_stream;

Anything stopping the driver from returning
msm_dp_ctrl_get_stream_cnt(dp->ctrl) here? Why do we need to cache it?

Got it. Will move it next patchset.

+}
+
  static int msm_dp_display_probe(struct platform_device *pdev)
  {
        int rc = 0;
diff --git a/drivers/gpu/drm/msm/dp/dp_display.h 
b/drivers/gpu/drm/msm/dp/dp_display.h
index 43ed79093e24..d3d4ab98089d 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.h
+++ b/drivers/gpu/drm/msm/dp/dp_display.h
@@ -26,6 +26,7 @@ struct msm_dp {
        bool psr_supported;
  };

+int msm_dp_get_mst_max_stream(struct msm_dp *msm_dp_display);

  int msm_dp_display_get_modes(struct msm_dp *msm_dp_display);
  bool msm_dp_display_check_video_test(struct msm_dp *msm_dp_display);
  int msm_dp_display_get_test_bpp(struct msm_dp *msm_dp_display);

--
2.43.0