From: Bhaskar Reddy Valluru <[email protected]> Add the GPU and GMU nodes describing the register maps, interrupts, clocks, power domains, IOMMU, interconnect paths and the OPP tables. The GPU node is left disabled here and is enabled by the board devicetrees.
Signed-off-by: Bhaskar Reddy Valluru <[email protected]> Signed-off-by: Akhil P Oommen <[email protected]> --- arch/arm64/boot/dts/qcom/maili.dtsi | 309 ++++++++++++++++++++++++++++++++++++ 1 file changed, 309 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/maili.dtsi b/arch/arm64/boot/dts/qcom/maili.dtsi index 886d307e536b..27558fbc307f 100644 --- a/arch/arm64/boot/dts/qcom/maili.dtsi +++ b/arch/arm64/boot/dts/qcom/maili.dtsi @@ -3776,6 +3776,250 @@ tcsrcc: clock-controller@3b13040 { #reset-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-44041400", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x6c000>, + <0x0 0x03d9e000 0x0 0x2000>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem"; + + interrupts = <GIC_ESPI 364 IRQ_TYPE_LEVEL_HIGH>; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + #cooling-cells = <2>; + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + + status = "disabled"; + + gpu_zap_shader: zap-shader { + memory-region = <&gpu_microcode_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2-adreno", + "operating-points-v2"; + + opp-1450000000 { + opp-hz = /bits/ 64 <1450000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3_1>; + opp-peak-kBps = <20832031>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0x88295ffd>; + }; + + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3_0>; + opp-peak-kBps = <20832031>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0x88295ffd>; + }; + + opp-1350000000 { + opp-hz = /bits/ 64 <1350000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; + opp-peak-kBps = <20832031>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0xa8295ffd>; + }; + + opp-1275000000 { + opp-hz = /bits/ 64 <1275000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1_1>; + opp-peak-kBps = <18671875>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0xa82a5ffd>; + }; + + opp-1201000000 { + opp-hz = /bits/ 64 <1201000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1_0>; + opp-peak-kBps = <18671875>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0xa82b5ffd>; + }; + + opp-1126000000 { + opp-hz = /bits/ 64 <1126000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + opp-peak-kBps = <16500000>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0xa82b5ffd>; + }; + + opp-1025000000 { + opp-hz = /bits/ 64 <1025000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + opp-peak-kBps = <16500000>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0xa82b5ffd>; + }; + + opp-951000000 { + opp-hz = /bits/ 64 <951000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + opp-peak-kBps = <12449218>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0xa82b5ffd>; + }; + + opp-843000000 { + opp-hz = /bits/ 64 <843000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + opp-peak-kBps = <12449218>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0xa82c5ffd>; + }; + + opp-801000000 { + opp-hz = /bits/ 64 <801000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2_0>; + opp-peak-kBps = <12449218>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0x882d5ffd>; + }; + + opp-759000000 { + opp-hz = /bits/ 64 <759000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; + opp-peak-kBps = <12449218>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0xa82d5ffd>; + }; + + opp-693000000 { + opp-hz = /bits/ 64 <693000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-peak-kBps = <12449218>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0x882e5ffd>; + }; + + opp-636000000 { + opp-hz = /bits/ 64 <636000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; + opp-peak-kBps = <10687500>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0x882f5ffd>; + }; + + opp-578000000 { + opp-hz = /bits/ 64 <578000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + opp-peak-kBps = <8171875>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0xe02a5ffd>; + }; + + opp-539000000 { + opp-hz = /bits/ 64 <539000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>; + opp-peak-kBps = <8171875>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0xc02c5ffd>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; + opp-peak-kBps = <8171875>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0xc02d5ffd>; + }; + + opp-461000000 { + opp-hz = /bits/ 64 <461000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L0>; + opp-peak-kBps = <8171875>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0xc02e5ffd>; + }; + + opp-422000000 { + opp-hz = /bits/ 64 <422000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + opp-peak-kBps = <6074218>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0xe82f5ffd>; + }; + + opp-390000000 { + opp-hz = /bits/ 64 <390000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; + opp-peak-kBps = <6074218>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0xe82f5ffd>; + }; + + opp-357000000 { + opp-hz = /bits/ 64 <357000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0_0>; + opp-peak-kBps = <6074218>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0xe82f5ffd>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; + opp-peak-kBps = <5285156>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0xe82f5ffd>; + }; + + opp-274000000 { + opp-hz = /bits/ 64 <274000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1_1>; + opp-peak-kBps = <5285156>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0xe82f5ffd>; + }; + + opp-222000000 { + opp-hz = /bits/ 64 <222000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; + opp-peak-kBps = <2136718>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0xe82f5ffd>; + }; + + opp-190000000 { + opp-hz = /bits/ 64 <190000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2_1>; + opp-peak-kBps = <2136718>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0xe82f5ffd>; + }; + + opp-157000000 { + opp-hz = /bits/ 64 <157000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>; + opp-peak-kBps = <2136718>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0xe82f5ffd>; + }; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3_0>; + opp-peak-kBps = <2136718>; + opp-supported-hw = <0x0f>; + qcom,opp-acd-level = <0xe82f5ffd>; + }; + }; + }; + gxclkctl: clock-controller@3d64000 { compatible = "qcom,maili-gxclkctl", "qcom,kaanapali-gxclkctl"; reg = <0x0 0x03d64000 0x0 0x6000>; @@ -3787,6 +4031,71 @@ gxclkctl: clock-controller@3d64000 { #power-domain-cells = <1>; }; + gmu: gmu@3d6c000 { + compatible = "qcom,adreno-gmu-845.0", "qcom,adreno-gmu"; + reg = <0x0 0x03d6c000 0x0 0x32000>; + reg-names = "gmu"; + + interrupts = <GIC_ESPI 368 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 369 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_MXG_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>; + clock-names = "gmu", + "cxo", + "smmu_vote", + "ahb", + "mxg_ahb", + "hub"; + + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gxclkctl GX_CLKCTL_GX_GDSC>, + <&gpucc GPU_CC_MXG_GDSC>; + power-domain-names = "cx", + "gx", + "gmu_mx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-556000000 { + opp-hz = /bits/ 64 <556000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>; + }; + + opp-788000000 { + opp-hz = /bits/ 64 <788000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + opp-825000000 { + opp-hz = /bits/ 64 <825000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + opp-880000000 { + opp-hz = /bits/ 64 <880000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + opp-917000000 { + opp-hz = /bits/ 64 <917000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,maili-gpucc"; reg = <0x0 0x03d90000 0x0 0x9800>; -- 2.55.0
