diff -Nur plex86-old/Makefile.in plex86/Makefile.in
--- plex86-old/Makefile.in	Sun Mar 26 19:30:27 2000
+++ plex86/Makefile.in	Sat Apr  1 17:08:09 2000
@@ -43,6 +43,7 @@
 	$(MAKE) -C user dist-clean
 	$(MAKE) -C kernel dist-clean
 	$(MAKE) -C guest dist-clean
+	$(MAKE) -C docs dist-clean
 	/bin/rm -f config.status config.cache config.log
 	/bin/rm -f Makefile config.h
 
diff -Nur plex86-old/docs/output/README plex86/docs/output/README
--- plex86-old/docs/output/README	Thu Jan  1 01:00:00 1970
+++ plex86/docs/output/README	Sat Apr  1 17:10:08 2000
@@ -0,0 +1 @@
+This directory is generated dynamically - do not alter.
diff -Nur plex86-old/docs/txt/Makefile plex86/docs/txt/Makefile
--- plex86-old/docs/txt/Makefile	Thu Mar 30 22:13:44 2000
+++ plex86/docs/txt/Makefile	Sat Apr  1 17:09:55 2000
@@ -12,5 +12,5 @@
 	rm -f paper-19991129a.ps
 
 clean:
-	rm *.ps
-	rm *.html
+	rm -f *.ps
+	rm -f *.html
diff -Nur plex86-old/kernel/fetchdecode.c plex86/kernel/fetchdecode.c
--- plex86-old/kernel/fetchdecode.c	Sun Mar 26 18:52:47 2000
+++ plex86/kernel/fetchdecode.c	Sat Apr  1 13:54:05 2000
@@ -21,1776 +21,1959 @@
  */
 
 
-
 #include "plex86.h"
 #include "fetchdecode.h"
 
 
+static const unsigned sreg_mod00_rm16[8] =
+{
+    SEG_REG_DS,
+    SEG_REG_DS,
+    SEG_REG_SS,
+    SEG_REG_SS,
+    SEG_REG_DS,
+    SEG_REG_DS,
+    SEG_REG_DS,
+    SEG_REG_DS
+};
 
 
-static const unsigned sreg_mod00_rm16[8] = {
-  SEG_REG_DS,
-  SEG_REG_DS,
-  SEG_REG_SS,
-  SEG_REG_SS,
-  SEG_REG_DS,
-  SEG_REG_DS,
-  SEG_REG_DS,
-  SEG_REG_DS
-  };
-
-static const unsigned sreg_mod01_rm16[8] = {
-  SEG_REG_DS,
-  SEG_REG_DS,
-  SEG_REG_SS,
-  SEG_REG_SS,
-  SEG_REG_DS,
-  SEG_REG_DS,
-  SEG_REG_SS,
-  SEG_REG_DS
-  };
-
-static const unsigned sreg_mod10_rm16[8] = {
-  SEG_REG_DS,
-  SEG_REG_DS,
-  SEG_REG_SS,
-  SEG_REG_SS,
-  SEG_REG_DS,
-  SEG_REG_DS,
-  SEG_REG_SS,
-  SEG_REG_DS
-  };
-
-  // the default segment to use for a one-byte modrm with mod==01b
-  // and rm==i
-  //
-static const unsigned sreg_mod01_rm32[8] = {
-  SEG_REG_DS,
-  SEG_REG_DS,
-  SEG_REG_DS,
-  SEG_REG_DS,
-  SEG_REG_NULL,
-    // this entry should never be accessed
-    // (escape to 2-byte)
-  SEG_REG_SS,
-  SEG_REG_DS,
-  SEG_REG_DS
-  };
-
-  // the default segment to use for a one-byte modrm with mod==10b
-  // and rm==i
-  //
-static const unsigned sreg_mod10_rm32[8] = {
-  SEG_REG_DS,
-  SEG_REG_DS,
-  SEG_REG_DS,
-  SEG_REG_DS,
-  SEG_REG_NULL,
-    // this entry should never be accessed
-    // (escape to 2-byte)
-  SEG_REG_SS,
-  SEG_REG_DS,
-  SEG_REG_DS
-  };
-
-
-  // the default segment to use for a two-byte modrm with mod==00b
-  // and base==i
-  //
-static const unsigned sreg_mod0_base32[8] = {
-  SEG_REG_DS,
-  SEG_REG_DS,
-  SEG_REG_DS,
-  SEG_REG_DS,
-  SEG_REG_SS,
-  SEG_REG_DS,
-  SEG_REG_DS,
-  SEG_REG_DS
-  };
-
-  // the default segment to use for a two-byte modrm with
-  // mod==01b or mod==10b and base==i
-static const unsigned sreg_mod1or2_base32[8] = {
-  SEG_REG_DS,
-  SEG_REG_DS,
-  SEG_REG_DS,
-  SEG_REG_DS,
-  SEG_REG_SS,
-  SEG_REG_SS,
-  SEG_REG_DS,
-  SEG_REG_DS
-  };
-
-
-static Bit16u groupNattr[NumGroups][8] = {
-// G1EbIb
-  {
-  /* 0 */  Immediate_Ib, // ADD_EbIb
-  /* 1 */  Immediate_Ib, // OR_EbIb
-  /* 2 */  Immediate_Ib, // ADC_EbIb
-  /* 3 */  Immediate_Ib, // SBB_EbIb
-  /* 4 */  Immediate_Ib, // AND_EbIb
-  /* 5 */  Immediate_Ib, // SUB_EbIb
-  /* 6 */  Immediate_Ib, // XOR_EbIb
-  /* 7 */  Immediate_Ib, // CMP_EbIb
-  },
-
-// G1Ew
-  {
-  // attributes defined in main area
-  /* 0 */  0, // ADD_EwIw
-  /* 1 */  0, // OR_EwIw
-  /* 2 */  0, // ADC_EwIw
-  /* 3 */  0, // SBB_EwIw
-  /* 4 */  0, // AND_EwIw
-  /* 5 */  0, // SUB_EwIw
-  /* 6 */  0, // XOR_EwIw
-  /* 7 */  0, // CMP_EwIw
-  }, 
-
-// G1Ed
-  {
-  // attributes defined in main area
-  /* 0 */  0, // ADD_EdId
-  /* 1 */  0, // OR_EdId
-  /* 2 */  0, // ADC_EdId
-  /* 3 */  0, // SBB_EdId
-  /* 4 */  0, // AND_EdId
-  /* 5 */  0, // SUB_EdId
-  /* 6 */  0, // XOR_EdId
-  /* 7 */  0, // CMP_EdId
-  }, 
-
-// G2Eb
-  {
-  // attributes defined in main area
-  /* 0 */  0, // ROL_Eb
-  /* 1 */  0, // ROR_Eb
-  /* 2 */  0, // RCL_Eb
-  /* 3 */  0, // RCR_Eb
-  /* 4 */  0, // SHL_Eb
-  /* 5 */  0, // SHR_Eb
-  /* 6 */  0, // SHL_Eb
-  /* 7 */  0, // SAR_Eb
-  },
-
-// G2Ew
-  {
-  // attributes defined in main area
-  /* 0 */  0, // ROL_Ew
-  /* 1 */  0, // ROR_Ew
-  /* 2 */  0, // RCL_Ew
-  /* 3 */  0, // RCR_Ew
-  /* 4 */  0, // SHL_Ew
-  /* 5 */  0, // SHR_Ew
-  /* 6 */  0, // SHL_Ew
-  /* 7 */  0, // SAR_Ew
-  },
-
-// G2Ed
-  {
-  // attributes defined in main area
-  /* 0 */  0, // ROL_Ed
-  /* 1 */  0, // ROR_Ed
-  /* 2 */  0, // RCL_Ed
-  /* 3 */  0, // RCR_Ed
-  /* 4 */  0, // SHL_Ed
-  /* 5 */  0, // SHR_Ed
-  /* 6 */  0, // SHL_Ed
-  /* 7 */  0, // SAR_Ed
-  }, 
-
-// G3Eb
-  {
-  /* 0 */  Immediate_Ib, // TEST_EbIb
-  /* 1 */  Immediate_Ib, // TEST_EbIb
-  /* 2 */  0, // NOT_Eb
-  /* 3 */  0, // NEG_Eb
-  /* 4 */  0, // MUL_ALEb
-  /* 5 */  0, // IMUL_ALEb
-  /* 6 */  0, // DIV_ALEb
-  /* 7 */  0, // IDIV_ALEb
-  },
-
-// G3Ew
-  {
-  /* 0 */  Immediate_Iw, // TEST_EwIw
-  /* 1 */  Immediate_Iw, // TEST_EwIw
-  /* 2 */  0, // NOT_Ew
-  /* 3 */  0, // NEG_Ew
-  /* 4 */  0, // MUL_AXEw
-  /* 5 */  0, // IMUL_AXEw
-  /* 6 */  0, // DIV_AXEw
-  /* 7 */  0, // IDIV_AXEw
-  },
-
-// G3Ed
-  {
-  /* 0 */  Immediate_Iv, // TEST_EdId
-  /* 1 */  Immediate_Iv, // TEST_EdId
-  /* 2 */  0, // NOT_Ed
-  /* 3 */  0, // NEG_Ed
-  /* 4 */  0, // MUL_EAXEd
-  /* 5 */  0, // IMUL_EAXEd
-  /* 6 */  0, // DIV_EAXEd
-  /* 7 */  0, // IDIV_EAXEd
-  },
-
-// G4
-  {
-  /* 0 */  0, // INC_Eb
-  /* 1 */  0, // DEC_Eb
-  /* 2 */  InvalidOpcode,
-  /* 3 */  InvalidOpcode,
-  /* 4 */  InvalidOpcode,
-  /* 5 */  InvalidOpcode,
-  /* 6 */  InvalidOpcode,
-  /* 7 */  InvalidOpcode,
-  },
-
-// G5w
-  {
-  // attributes defined in main area
-  /* 0 */  0, // INC_Ew
-  /* 1 */  0, // DEC_Ew
-  /* 2 */  0, // CALL_Ew
-  /* 3 */  0, // CALL16_Ep
-  /* 4 */  0 | UCBranch, // JMP_Ew
-  /* 5 */  0 | UCBranch, // JMP16_Ep
-  /* 6 */  0, // PUSH_Ew
-  /* 7 */  InvalidOpcode,
-  },
-
-// G5d
-  {
-  // attributes defined in main area
-  /* 0 */  0, // INC_Ed
-  /* 1 */  0, // DEC_Ed
-  /* 2 */  0, // CALL_Ed
-  /* 3 */  0, // CALL32_Ep
-  /* 4 */  0 | UCBranch, // JMP_Ed
-  /* 5 */  0 | UCBranch, // JMP32_Ep
-  /* 6 */  0, // PUSH_Ed
-  /* 7 */  InvalidOpcode,
-  },
-
-// G6
-  {
-  // attributes defined in main area
-  /* 0 */  0, // SLDT_Ew
-  /* 1 */  0, // STR_Ew
-  /* 2 */  0, // LLDT_Ew
-  /* 3 */  0, // LTR_Ew
-  /* 4 */  0, // VERR_Ew
-  /* 5 */  0, // VERW_Ew
-  /* 6 */  InvalidOpcode,
-  /* 7 */  InvalidOpcode,
-  },
-
-// G7
-  {
-  /* 0 */  0, // SGDT_Ms
-  /* 1 */  0, // SIDT_Ms
-  /* 2 */  0, // LGDT_Ms
-  /* 3 */  0, // LIDT_Ms
-  /* 4 */  0, // SMSW_Ew
-  /* 5 */  InvalidOpcode,
-  /* 6 */  0, // LMSW_Ew
-  /* 7 */  0, // INVLPG
-  },
-
-
-// G8EvIb
-  {
-  /* 0 */  InvalidOpcode,
-  /* 1 */  InvalidOpcode,
-  /* 2 */  InvalidOpcode,
-  /* 3 */  InvalidOpcode,
-  /* 4 */  Immediate_Ib, // BT_EvIb
-  /* 5 */  Immediate_Ib, // BTS_EvIb
-  /* 6 */  Immediate_Ib, // BTR_EvIb
-  /* 7 */  Immediate_Ib, // BTC_EvIb
-  },
-
-// G9
-  {
-  /* 0 */  InvalidOpcode,
-  /* 1 */  0, // CMPXCHG8B
-  /* 2 */  InvalidOpcode,
-  /* 3 */  InvalidOpcode,
-  /* 4 */  InvalidOpcode,
-  /* 5 */  InvalidOpcode,
-  /* 6 */  InvalidOpcode,
-  /* 7 */  InvalidOpcode,
-  },
+static const unsigned sreg_mod01_rm16[8] =
+{
+    SEG_REG_DS,
+    SEG_REG_DS,
+    SEG_REG_SS,
+    SEG_REG_SS,
+    SEG_REG_DS,
+    SEG_REG_DS,
+    SEG_REG_SS,
+    SEG_REG_DS
 };
 
 
-// 512 entries for 16bit mode
-// 512 entries for 32bit mode
+static const unsigned sreg_mod10_rm16[8] =
+{
+    SEG_REG_DS,
+    SEG_REG_DS,
+    SEG_REG_SS,
+    SEG_REG_SS,
+    SEG_REG_DS,
+    SEG_REG_DS,
+    SEG_REG_SS,
+    SEG_REG_DS
+};
 
-static Bit16u OpcodeInfo[512*2] = {
-  // 512 entries for 16bit mode
-  /* 00 */  Another, // ADD_EbGb
-  /* 01 */  Another, // ADD_EwGw
-  /* 02 */  Another, // ADD_GbEb
-  /* 03 */  Another, // ADD_GwEw
-  /* 04 */  Immediate_Ib, // ADD_ALIb
-  /* 05 */  Immediate_Iv, // ADD_AXIw
-  /* 06 */  0, // PUSH_ES
-  /* 07 */  0, // POP_ES
-  /* 08 */  Another, // OR_EbGb
-  /* 09 */  Another, // OR_EwGw
-  /* 0A */  Another, // OR_GbEb
-  /* 0B */  Another, // OR_GwEw
-  /* 0C */  Immediate_Ib, // OR_ALIb
-  /* 0D */  Immediate_Iv, // OR_AXIw
-  /* 0E */  0, // PUSH_CS
-  /* 0F */  Another, // 2-byte escape
-  /* 10 */  Another, // ADC_EbGb
-  /* 11 */  Another, // ADC_EwGw
-  /* 12 */  Another, // ADC_GbEb
-  /* 13 */  Another, // ADC_GwEw
-  /* 14 */  Immediate_Ib, // ADC_ALIb
-  /* 15 */  Immediate_Iv, // ADC_AXIw
-  /* 16 */  0, // PUSH_SS
-  /* 17 */  0, // POP_SS
-  /* 18 */  Another, // SBB_EbGb
-  /* 19 */  Another, // SBB_EwGw
-  /* 1A */  Another, // SBB_GbEb
-  /* 1B */  Another, // SBB_GwEw
-  /* 1C */  Immediate_Ib, // SBB_ALIb
-  /* 1D */  Immediate_Iv, // SBB_AXIw
-  /* 1E */  0, // PUSH_DS
-  /* 1F */  0, // POP_DS
-  /* 20 */  Another, // AND_EbGb
-  /* 21 */  Another, // AND_EwGw
-  /* 22 */  Another, // AND_GbEb
-  /* 23 */  Another, // AND_GwEw
-  /* 24 */  Immediate_Ib, // AND_ALIb
-  /* 25 */  Immediate_Iv, // AND_AXIw
-  /* 26 */  Prefix | Another, // ES:
-  /* 27 */  0, // DAA
-  /* 28 */  Another, // SUB_EbGb
-  /* 29 */  Another, // SUB_EwGw
-  /* 2A */  Another, // SUB_GbEb
-  /* 2B */  Another, // SUB_GwEw
-  /* 2C */  Immediate_Ib, // SUB_ALIb
-  /* 2D */  Immediate_Iv, // SUB_AXIw
-  /* 2E */  Prefix | Another, // CS:
-  /* 2F */  0, // DAS
-  /* 30 */  Another, // XOR_EbGb
-  /* 31 */  Another, // XOR_EwGw
-  /* 32 */  Another, // XOR_GbEb
-  /* 33 */  Another, // XOR_GwEw
-  /* 34 */  Immediate_Ib, // XOR_ALIb
-  /* 35 */  Immediate_Iv, // XOR_AXIw
-  /* 36 */  Prefix | Another, // SS:
-  /* 37 */  0, // AAA
-  /* 38 */  Another, // CMP_EbGb
-  /* 39 */  Another, // CMP_EwGw
-  /* 3A */  Another, // CMP_GbEb
-  /* 3B */  Another, // CMP_GwEw
-  /* 3C */  Immediate_Ib, // CMP_ALIb
-  /* 3D */  Immediate_Iv, // CMP_AXIw
-  /* 3E */  Prefix | Another, // DS:
-  /* 3F */  0, // AAS
-  /* 40 */  0, // INC_RX
-  /* 41 */  0, // INC_RX
-  /* 42 */  0, // INC_RX
-  /* 43 */  0, // INC_RX
-  /* 44 */  0, // INC_RX
-  /* 45 */  0, // INC_RX
-  /* 46 */  0, // INC_RX
-  /* 47 */  0, // INC_RX
-  /* 48 */  0, // DEC_RX
-  /* 49 */  0, // DEC_RX
-  /* 4A */  0, // DEC_RX
-  /* 4B */  0, // DEC_RX
-  /* 4C */  0, // DEC_RX
-  /* 4D */  0, // DEC_RX
-  /* 4E */  0, // DEC_RX
-  /* 4F */  0, // DEC_RX
-  /* 50 */  0, // PUSH_RX
-  /* 51 */  0, // PUSH_RX
-  /* 52 */  0, // PUSH_RX
-  /* 53 */  0, // PUSH_RX
-  /* 54 */  0, // PUSH_RX
-  /* 55 */  0, // PUSH_RX
-  /* 56 */  0, // PUSH_RX
-  /* 57 */  0, // PUSH_RX
-  /* 58 */  0, // POP_RX
-  /* 59 */  0, // POP_RX
-  /* 5A */  0, // POP_RX
-  /* 5B */  0, // POP_RX
-  /* 5C */  0, // POP_RX
-  /* 5D */  0, // POP_RX
-  /* 5E */  0, // POP_RX
-  /* 5F */  0, // POP_RX
-  /* 60 */  0, // PUSHAD16
-  /* 61 */  0, // POPAD16
-  /* 62 */  Another, // BOUND_GvMa
-  /* 63 */  Another, // ARPL_EwGw
-  /* 64 */  Prefix | Another, // FS:
-  /* 65 */  Prefix | Another, // GS:
-  /* 66 */  Prefix | Another, // OS:
-  /* 67 */  Prefix | Another, // AS:
-  /* 68 */  Immediate_Iv, // PUSH_Iw
-  /* 69 */  Another | Immediate_Iv, // IMUL_GwEwIw
-  /* 6A */  Immediate_Ib_SE, // PUSH_Iw
-  /* 6B */  Another | Immediate_Ib_SE, // IMUL_GwEwIw
-  /* 6C */  Repeatable, // INSB_YbDX
-  /* 6D */  Repeatable, // INSW_YvDX
-  /* 6E */  Repeatable, // OUTSB_DXXb
-  /* 6F */  Repeatable, // OUTSW_DXXv
-  /* 70 */  Immediate_BrOff8, // JCC_Jw
-  /* 71 */  Immediate_BrOff8, // JCC_Jw
-  /* 72 */  Immediate_BrOff8, // JCC_Jw
-  /* 73 */  Immediate_BrOff8, // JCC_Jw
-  /* 74 */  Immediate_BrOff8, // JCC_Jw
-  /* 75 */  Immediate_BrOff8, // JCC_Jw
-  /* 76 */  Immediate_BrOff8, // JCC_Jw
-  /* 77 */  Immediate_BrOff8, // JCC_Jw
-  /* 78 */  Immediate_BrOff8, // JCC_Jw
-  /* 79 */  Immediate_BrOff8, // JCC_Jw
-  /* 7A */  Immediate_BrOff8, // JCC_Jw
-  /* 7B */  Immediate_BrOff8, // JCC_Jw
-  /* 7C */  Immediate_BrOff8, // JCC_Jw
-  /* 7D */  Immediate_BrOff8, // JCC_Jw
-  /* 7E */  Immediate_BrOff8, // JCC_Jw
-  /* 7F */  Immediate_BrOff8, // JCC_Jw
-  /* 80 */  Another | GroupN | PutGroupIndex(G1EbIb),
-  /* 81 */  Another | GroupN | Immediate_Iv | PutGroupIndex(G1Ew),
-  /* 82 */  Another | GroupN | PutGroupIndex(G1EbIb),
-  /* 83 */  Another | GroupN | Immediate_Ib_SE | PutGroupIndex(G1Ew),
-  /* 84 */  Another, // TEST_EbGb
-  /* 85 */  Another, // TEST_EwGw
-  /* 86 */  Another, // XCHG_EbGb
-  /* 87 */  Another, // XCHG_EwGw
-  /* 88 */  Another, // MOV_EbGb
-  /* 89 */  Another, // MOV_EwGw
-  /* 8A */  Another, // MOV_GbEb
-  /* 8B */  Another, // MOV_GwEw
-  /* 8C */  Another, // MOV_EwSw
-  /* 8D */  Another, // LEA_GwM
-  /* 8E */  Another, // MOV_SwEw
-  /* 8F */  Another, // POP_Ew
-  /* 90 */  0, // NOP
-  /* 91 */  0, // XCHG_RXAX
-  /* 92 */  0, // XCHG_RXAX
-  /* 93 */  0, // XCHG_RXAX
-  /* 94 */  0, // XCHG_RXAX
-  /* 95 */  0, // XCHG_RXAX
-  /* 96 */  0, // XCHG_RXAX
-  /* 97 */  0, // XCHG_RXAX
-  /* 98 */  0, // CBW
-  /* 99 */  0, // CWD
-  /* 9A */  Immediate_IvIw, // CALL16_Ap
-  /* 9B */  0, // FWAIT
-  /* 9C */  0, // PUSHF_Fv
-  /* 9D */  0, // POPF_Fv
-  /* 9E */  0, // SAHF
-  /* 9F */  0, // LAHF
-  /* A0 */  Immediate_O, // MOV_ALOb
-  /* A1 */  Immediate_O, // MOV_AXOw
-  /* A2 */  Immediate_O, // MOV_ObAL
-  /* A3 */  Immediate_O, // MOV_OwAX
-  /* A4 */  Repeatable, // MOVSB_XbYb
-  /* A5 */  Repeatable, // MOVSW_XvYv
-  /* A6 */  Repeatable | RepeatableZF, // CMPSB_XbYb
-  /* A7 */  Repeatable | RepeatableZF, // CMPSW_XvYv
-  /* A8 */  Immediate_Ib, // TEST_ALIb
-  /* A9 */  Immediate_Iv, // TEST_AXIw
-  /* AA */  Repeatable, // STOSB_YbAL
-  /* AB */  Repeatable, // STOSW_YveAX
-  /* AC */  Repeatable, // LODSB_ALXb
-  /* AD */  Repeatable, // LODSW_eAXXv
-  /* AE */  Repeatable | RepeatableZF, // SCASB_ALXb
-  /* AF */  Repeatable | RepeatableZF, // SCASW_eAXXv
-  /* B0 */  Immediate_Ib, // MOV_RLIb
-  /* B1 */  Immediate_Ib, // MOV_RLIb
-  /* B2 */  Immediate_Ib, // MOV_RLIb
-  /* B3 */  Immediate_Ib, // MOV_RLIb
-  /* B4 */  Immediate_Ib, // MOV_RHIb
-  /* B5 */  Immediate_Ib, // MOV_RHIb
-  /* B6 */  Immediate_Ib, // MOV_RHIb
-  /* B7 */  Immediate_Ib, // MOV_RHIb
-  /* B8 */  Immediate_Iv, // MOV_RXIw
-  /* B9 */  Immediate_Iv, // MOV_RXIw
-  /* BA */  Immediate_Iv, // MOV_RXIw
-  /* BB */  Immediate_Iv, // MOV_RXIw
-  /* BC */  Immediate_Iv, // MOV_RXIw
-  /* BD */  Immediate_Iv, // MOV_RXIw
-  /* BE */  Immediate_Iv, // MOV_RXIw
-  /* BF */  Immediate_Iv, // MOV_RXIw
-  /* C0 */  Another | GroupN | Immediate_Ib | PutGroupIndex(G2Eb),
-  /* C1 */  Another | GroupN | Immediate_Ib | PutGroupIndex(G2Ew),
-  /* C2 */  Immediate_Iw | UCBranch, // RETnear16_Iw
-  /* C3 */  0 | UCBranch, // RETnear16
-  /* C4 */  Another, // LES_GvMp
-  /* C5 */  Another, // LDS_GvMp
-  /* C6 */  Another | Immediate_Ib, // MOV_EbIb
-  /* C7 */  Another | Immediate_Iv, // MOV_EwIw
-  /* C8 */  Immediate_IwIb, // ENTER_IwIb
-  /* C9 */  0, // LEAVE
-  /* CA */  Immediate_Iw | UCBranch, // RETfar16_Iw
-  /* CB */  0 | UCBranch, // RETfar16
-  /* CC */  0, // INT3
-  /* CD */  Immediate_Ib, // INT_Ib
-  /* CE */  0, // INTO
-  /* CF */  0 | UCBranch, // IRET16
-  /* D0 */  Another | GroupN | PutGroupIndex(G2Eb),
-  /* D1 */  Another | GroupN | PutGroupIndex(G2Ew),
-  /* D2 */  Another | GroupN | PutGroupIndex(G2Eb),
-  /* D3 */  Another | GroupN | PutGroupIndex(G2Ew),
-  /* D4 */  Immediate_Ib, // AAM
-  /* D5 */  Immediate_Ib, // AAD
-  /* D6 */  0, // SALC
-  /* D7 */  0, // XLAT
-  /* D8 */  Another, // ESC0
-  /* D9 */  Another, // ESC1
-  /* DA */  Another, // ESC2
-  /* DB */  Another, // ESC3
-  /* DC */  Another, // ESC4
-  /* DD */  Another, // ESC5
-  /* DE */  Another, // ESC6
-  /* DF */  Another, // ESC7
-  /* E0 */  Immediate_BrOff8, // LOOPNE_Jb
-  /* E1 */  Immediate_BrOff8, // LOOPE_Jb
-  /* E2 */  Immediate_BrOff8, // LOOP_Jb
-  /* E3 */  Immediate_BrOff8, // JCXZ_Jb
-  /* E4 */  Immediate_Ib, // IN_ALIb
-  /* E5 */  Immediate_Ib, // IN_eAXIb
-  /* E6 */  Immediate_Ib, // OUT_IbAL
-  /* E7 */  Immediate_Ib, // OUT_IbeAX
-  /* E8 */  Immediate_BrOff16, // CALL_Aw
-  /* E9 */  Immediate_BrOff16 | UCBranch, // JMP_Jw
-  /* EA */  Immediate_IvIw | UCBranch, // JMP_Ap
-  /* EB */  Immediate_BrOff8 | UCBranch, // JMP_Jb
-  /* EC */  0, // IN_ALDX
-  /* ED */  0, // IN_eAXDX
-  /* EE */  0, // OUT_DXAL
-  /* EF */  0, // OUT_DXeAX
-  /* F0 */  Prefix | Another, // LOCK:
-  /* F1 */  0, // INT1
-  /* F2 */  Prefix | Another, // REPNE/REPNZ:
-  /* F3 */  Prefix | Another, // REP, REPE/REPZ:
-  /* F4 */  0, // HLT
-  /* F5 */  0, // CMC
-  /* F6 */  Another | GroupN | PutGroupIndex(G3Eb),
-  /* F7 */  Another | GroupN | PutGroupIndex(G3Ew),
-  /* F8 */  0, // CLC
-  /* F9 */  0, // STC
-  /* FA */  0, // CLI
-  /* FB */  0, // STI
-  /* FC */  0, // CLD
-  /* FD */  0, // STD
-  /* FE */  Another | GroupN | PutGroupIndex(G4),
-  /* FF */  Another | GroupN | PutGroupIndex(G5w),
- 
-  /* 0F 00 */  Another | GroupN | PutGroupIndex(G6),
-  /* 0F 01 */  Another | GroupN | PutGroupIndex(G7),
-  /* 0F 02 */  Another, // LAR_GvEw
-  /* 0F 03 */  Another, // LSL_GvEw
-  /* 0F 04 */  InvalidOpcode, 
-  /* 0F 05 */  0, // LOADALL
-  /* 0F 06 */  0, // CLTS
-  /* 0F 07 */  InvalidOpcode, 
-  /* 0F 08 */  0, // INVD
-  /* 0F 09 */  0, // WBINVD
-  /* 0F 0A */  InvalidOpcode, 
-  /* 0F 0B */  InvalidOpcode, 
-  /* 0F 0C */  InvalidOpcode, 
-  /* 0F 0D */  InvalidOpcode, 
-  /* 0F 0E */  InvalidOpcode, 
-  /* 0F 0F */  InvalidOpcode, 
-  /* 0F 10 */  InvalidOpcode, 
-  /* 0F 11 */  InvalidOpcode, 
-  /* 0F 12 */  InvalidOpcode, 
-  /* 0F 13 */  InvalidOpcode, 
-  /* 0F 14 */  InvalidOpcode, 
-  /* 0F 15 */  InvalidOpcode, 
-  /* 0F 16 */  InvalidOpcode, 
-  /* 0F 17 */  InvalidOpcode, 
-  /* 0F 18 */  InvalidOpcode, 
-  /* 0F 19 */  InvalidOpcode, 
-  /* 0F 1A */  InvalidOpcode, 
-  /* 0F 1B */  InvalidOpcode, 
-  /* 0F 1C */  InvalidOpcode, 
-  /* 0F 1D */  InvalidOpcode, 
-  /* 0F 1E */  InvalidOpcode, 
-  /* 0F 1F */  InvalidOpcode, 
-  /* 0F 20 */  Another, // MOV_RdCd
-  /* 0F 21 */  Another, // MOV_RdDd
-  /* 0F 22 */  Another, // MOV_CdRd
-  /* 0F 23 */  Another, // MOV_DdRd
-  /* 0F 24 */  Another, // MOV_RdTd
-  /* 0F 25 */  InvalidOpcode, 
-  /* 0F 26 */  Another, // MOV_TdRd
-  /* 0F 27 */  InvalidOpcode, 
-  /* 0F 28 */  InvalidOpcode, 
-  /* 0F 29 */  InvalidOpcode, 
-  /* 0F 2A */  InvalidOpcode, 
-  /* 0F 2B */  InvalidOpcode, 
-  /* 0F 2C */  InvalidOpcode, 
-  /* 0F 2D */  InvalidOpcode, 
-  /* 0F 2E */  InvalidOpcode, 
-  /* 0F 2F */  InvalidOpcode, 
-  /* 0F 30 */  0, // WRMSR
-  /* 0F 31 */  0, // RDTSC
-  /* 0F 32 */  0, // RDMSR
-  /* 0F 33 */  InvalidOpcode, 
-  /* 0F 34 */  InvalidOpcode, 
-  /* 0F 35 */  InvalidOpcode, 
-  /* 0F 36 */  InvalidOpcode, 
-  /* 0F 37 */  InvalidOpcode, 
-  /* 0F 38 */  InvalidOpcode, 
-  /* 0F 39 */  InvalidOpcode, 
-  /* 0F 3A */  InvalidOpcode, 
-  /* 0F 3B */  InvalidOpcode, 
-  /* 0F 3C */  InvalidOpcode, 
-  /* 0F 3D */  InvalidOpcode, 
-  /* 0F 3E */  InvalidOpcode, 
-  /* 0F 3F */  InvalidOpcode, 
-  /* 0F 40 */  Another, // CMOV_GwEw
-  /* 0F 41 */  Another, // CMOV_GwEw
-  /* 0F 42 */  Another, // CMOV_GwEw
-  /* 0F 43 */  Another, // CMOV_GwEw
-  /* 0F 44 */  Another, // CMOV_GwEw
-  /* 0F 45 */  Another, // CMOV_GwEw
-  /* 0F 46 */  Another, // CMOV_GwEw
-  /* 0F 47 */  Another, // CMOV_GwEw
-  /* 0F 48 */  Another, // CMOV_GwEw
-  /* 0F 49 */  Another, // CMOV_GwEw
-  /* 0F 4A */  Another, // CMOV_GwEw
-  /* 0F 4B */  Another, // CMOV_GwEw
-  /* 0F 4C */  Another, // CMOV_GwEw
-  /* 0F 4D */  Another, // CMOV_GwEw
-  /* 0F 4E */  Another, // CMOV_GwEw
-  /* 0F 4F */  Another, // CMOV_GwEw
-  /* 0F 50 */  InvalidOpcode, 
-  /* 0F 51 */  InvalidOpcode, 
-  /* 0F 52 */  InvalidOpcode, 
-  /* 0F 53 */  InvalidOpcode, 
-  /* 0F 54 */  InvalidOpcode, 
-  /* 0F 55 */  InvalidOpcode, 
-  /* 0F 56 */  InvalidOpcode, 
-  /* 0F 57 */  InvalidOpcode, 
-  /* 0F 58 */  InvalidOpcode, 
-  /* 0F 59 */  InvalidOpcode, 
-  /* 0F 5A */  InvalidOpcode, 
-  /* 0F 5B */  InvalidOpcode, 
-  /* 0F 5C */  InvalidOpcode, 
-  /* 0F 5D */  InvalidOpcode, 
-  /* 0F 5E */  InvalidOpcode, 
-  /* 0F 5F */  InvalidOpcode, 
-  /* 0F 60 */  InvalidOpcode, 
-  /* 0F 61 */  InvalidOpcode, 
-  /* 0F 62 */  InvalidOpcode, 
-  /* 0F 63 */  InvalidOpcode, 
-  /* 0F 64 */  InvalidOpcode, 
-  /* 0F 65 */  InvalidOpcode, 
-  /* 0F 66 */  InvalidOpcode, 
-  /* 0F 67 */  InvalidOpcode, 
-  /* 0F 68 */  InvalidOpcode, 
-  /* 0F 69 */  InvalidOpcode, 
-  /* 0F 6A */  InvalidOpcode, 
-  /* 0F 6B */  InvalidOpcode, 
-  /* 0F 6C */  InvalidOpcode, 
-  /* 0F 6D */  InvalidOpcode, 
-  /* 0F 6E */  InvalidOpcode, 
-  /* 0F 6F */  InvalidOpcode, 
-  /* 0F 70 */  InvalidOpcode, 
-  /* 0F 71 */  InvalidOpcode, 
-  /* 0F 72 */  InvalidOpcode, 
-  /* 0F 73 */  InvalidOpcode, 
-  /* 0F 74 */  InvalidOpcode, 
-  /* 0F 75 */  InvalidOpcode, 
-  /* 0F 76 */  InvalidOpcode, 
-  /* 0F 77 */  InvalidOpcode, 
-  /* 0F 78 */  InvalidOpcode, 
-  /* 0F 79 */  InvalidOpcode, 
-  /* 0F 7A */  InvalidOpcode, 
-  /* 0F 7B */  InvalidOpcode, 
-  /* 0F 7C */  InvalidOpcode, 
-  /* 0F 7D */  InvalidOpcode, 
-  /* 0F 7E */  InvalidOpcode, 
-  /* 0F 7F */  InvalidOpcode, 
-  /* 0F 80 */  Immediate_BrOff16, // JCC_Jw
-  /* 0F 81 */  Immediate_BrOff16, // JCC_Jw
-  /* 0F 82 */  Immediate_BrOff16, // JCC_Jw
-  /* 0F 83 */  Immediate_BrOff16, // JCC_Jw
-  /* 0F 84 */  Immediate_BrOff16, // JCC_Jw
-  /* 0F 85 */  Immediate_BrOff16, // JCC_Jw
-  /* 0F 86 */  Immediate_BrOff16, // JCC_Jw
-  /* 0F 87 */  Immediate_BrOff16, // JCC_Jw
-  /* 0F 88 */  Immediate_BrOff16, // JCC_Jw
-  /* 0F 89 */  Immediate_BrOff16, // JCC_Jw
-  /* 0F 8A */  Immediate_BrOff16, // JCC_Jw
-  /* 0F 8B */  Immediate_BrOff16, // JCC_Jw
-  /* 0F 8C */  Immediate_BrOff16, // JCC_Jw
-  /* 0F 8D */  Immediate_BrOff16, // JCC_Jw
-  /* 0F 8E */  Immediate_BrOff16, // JCC_Jw
-  /* 0F 8F */  Immediate_BrOff16, // JCC_Jw
-  /* 0F 90 */  Another, // SETO_Eb
-  /* 0F 91 */  Another, // SETNO_Eb
-  /* 0F 92 */  Another, // SETB_Eb
-  /* 0F 93 */  Another, // SETNB_Eb
-  /* 0F 94 */  Another, // SETZ_Eb
-  /* 0F 95 */  Another, // SETNZ_Eb
-  /* 0F 96 */  Another, // SETBE_Eb
-  /* 0F 97 */  Another, // SETNBE_Eb
-  /* 0F 98 */  Another, // SETS_Eb
-  /* 0F 99 */  Another, // SETNS_Eb
-  /* 0F 9A */  Another, // SETP_Eb
-  /* 0F 9B */  Another, // SETNP_Eb
-  /* 0F 9C */  Another, // SETL_Eb
-  /* 0F 9D */  Another, // SETNL_Eb
-  /* 0F 9E */  Another, // SETLE_Eb
-  /* 0F 9F */  Another, // SETNLE_Eb
-  /* 0F A0 */  0, // PUSH_FS
-  /* 0F A1 */  0, // POP_FS
-  /* 0F A2 */  0, // CPUID
-  /* 0F A3 */  Another, // BT_EvGv
-  /* 0F A4 */  Another | Immediate_Ib, // SHLD_EwGw
-  /* 0F A5 */  Another, // SHLD_EwGw
-  /* 0F A6 */  0, // CMPXCHG_XBTS
-  /* 0F A7 */  0, // CMPXCHG_IBTS
-  /* 0F A8 */  0, // PUSH_GS
-  /* 0F A9 */  0, // POP_GS
-  /* 0F AA */  0, // RSM
-  /* 0F AB */  Another, // BTS_EvGv
-  /* 0F AC */  Another | Immediate_Ib, // SHRD_EwGw
-  /* 0F AD */  Another, // SHRD_EwGw
-  /* 0F AE */  InvalidOpcode, 
-  /* 0F AF */  Another, // IMUL_GwEw
-  /* 0F B0 */  Another, // CMPXCHG_EbGb
-  /* 0F B1 */  Another, // CMPXCHG_EwGw
-  /* 0F B2 */  Another, // LSS_GvMp
-  /* 0F B3 */  Another, // BTR_EvGv
-  /* 0F B4 */  Another, // LFS_GvMp
-  /* 0F B5 */  Another, // LGS_GvMp
-  /* 0F B6 */  Another, // MOVZX_GwEb
-  /* 0F B7 */  Another, // MOVZX_GwEw
-  /* 0F B8 */  InvalidOpcode, 
-  /* 0F B9 */  InvalidOpcode, 
-  /* 0F BA */  Another | GroupN | PutGroupIndex(G8EvIb),
-  /* 0F BB */  Another, // BTC_EvGv
-  /* 0F BC */  Another, // BSF_GvEv
-  /* 0F BD */  Another, // BSR_GvEv
-  /* 0F BE */  Another, // MOVSX_GwEb
-  /* 0F BF */  Another, // MOVSX_GwEw
-  /* 0F C0 */  Another, // XADD_EbGb
-  /* 0F C1 */  Another, // XADD_EwGw
-  /* 0F C2 */  InvalidOpcode, 
-  /* 0F C3 */  InvalidOpcode, 
-  /* 0F C4 */  InvalidOpcode, 
-  /* 0F C5 */  InvalidOpcode, 
-  /* 0F C6 */  InvalidOpcode, 
-  /* 0F C7 */  Another | GroupN | PutGroupIndex(G9),
-  /* 0F C8 */  0, // BSWAP_EAX
-  /* 0F C9 */  0, // BSWAP_ECX
-  /* 0F CA */  0, // BSWAP_EDX
-  /* 0F CB */  0, // BSWAP_EBX
-  /* 0F CC */  0, // BSWAP_ESP
-  /* 0F CD */  0, // BSWAP_EBP
-  /* 0F CE */  0, // BSWAP_ESI
-  /* 0F CF */  0, // BSWAP_EDI
-  /* 0F D0 */  InvalidOpcode, 
-  /* 0F D1 */  InvalidOpcode, 
-  /* 0F D2 */  InvalidOpcode, 
-  /* 0F D3 */  InvalidOpcode, 
-  /* 0F D4 */  InvalidOpcode, 
-  /* 0F D5 */  InvalidOpcode, 
-  /* 0F D6 */  InvalidOpcode, 
-  /* 0F D7 */  InvalidOpcode, 
-  /* 0F D8 */  InvalidOpcode, 
-  /* 0F D9 */  InvalidOpcode, 
-  /* 0F DA */  InvalidOpcode, 
-  /* 0F DB */  InvalidOpcode, 
-  /* 0F DC */  InvalidOpcode, 
-  /* 0F DD */  InvalidOpcode, 
-  /* 0F DE */  InvalidOpcode, 
-  /* 0F DF */  InvalidOpcode, 
-  /* 0F E0 */  InvalidOpcode, 
-  /* 0F E1 */  InvalidOpcode, 
-  /* 0F E2 */  InvalidOpcode, 
-  /* 0F E3 */  InvalidOpcode, 
-  /* 0F E4 */  InvalidOpcode, 
-  /* 0F E5 */  InvalidOpcode, 
-  /* 0F E6 */  InvalidOpcode, 
-  /* 0F E7 */  InvalidOpcode, 
-  /* 0F E8 */  InvalidOpcode, 
-  /* 0F E9 */  InvalidOpcode, 
-  /* 0F EA */  InvalidOpcode, 
-  /* 0F EB */  InvalidOpcode, 
-  /* 0F EC */  InvalidOpcode, 
-  /* 0F ED */  InvalidOpcode, 
-  /* 0F EE */  InvalidOpcode, 
-  /* 0F EF */  InvalidOpcode, 
-  /* 0F F0 */  InvalidOpcode, 
-  /* 0F F1 */  InvalidOpcode, 
-  /* 0F F2 */  InvalidOpcode, 
-  /* 0F F3 */  InvalidOpcode, 
-  /* 0F F4 */  InvalidOpcode, 
-  /* 0F F5 */  InvalidOpcode, 
-  /* 0F F6 */  InvalidOpcode, 
-  /* 0F F7 */  InvalidOpcode, 
-  /* 0F F8 */  InvalidOpcode, 
-  /* 0F F9 */  InvalidOpcode, 
-  /* 0F FA */  InvalidOpcode, 
-  /* 0F FB */  InvalidOpcode, 
-  /* 0F FC */  InvalidOpcode, 
-  /* 0F FD */  InvalidOpcode, 
-  /* 0F FE */  InvalidOpcode, 
-  /* 0F FF */  InvalidOpcode, 
- 
-  // 512 entries for 32bit mod 
-  /* 00 */  Another, // ADD_EbGb
-  /* 01 */  Another, // ADD_EdGd
-  /* 02 */  Another, // ADD_GbEb
-  /* 03 */  Another, // ADD_GdEd
-  /* 04 */  Immediate_Ib, // ADD_ALIb
-  /* 05 */  Immediate_Iv, // ADD_EAXId
-  /* 06 */  0, // PUSH_ES
-  /* 07 */  0, // POP_ES
-  /* 08 */  Another, // OR_EbGb
-  /* 09 */  Another, // OR_EdGd
-  /* 0A */  Another, // OR_GbEb
-  /* 0B */  Another, // OR_GdEd
-  /* 0C */  Immediate_Ib, // OR_ALIb
-  /* 0D */  Immediate_Iv, // OR_EAXId
-  /* 0E */  0, // PUSH_CS
-  /* 0F */  Another, // 2-byte escape
-  /* 10 */  Another, // ADC_EbGb
-  /* 11 */  Another, // ADC_EdGd
-  /* 12 */  Another, // ADC_GbEb
-  /* 13 */  Another, // ADC_GdEd
-  /* 14 */  Immediate_Ib, // ADC_ALIb
-  /* 15 */  Immediate_Iv, // ADC_EAXId
-  /* 16 */  0, // PUSH_SS
-  /* 17 */  0, // POP_SS
-  /* 18 */  Another, // SBB_EbGb
-  /* 19 */  Another, // SBB_EdGd
-  /* 1A */  Another, // SBB_GbEb
-  /* 1B */  Another, // SBB_GdEd
-  /* 1C */  Immediate_Ib, // SBB_ALIb
-  /* 1D */  Immediate_Iv, // SBB_EAXId
-  /* 1E */  0, // PUSH_DS
-  /* 1F */  0, // POP_DS
-  /* 20 */  Another, // AND_EbGb
-  /* 21 */  Another, // AND_EdGd
-  /* 22 */  Another, // AND_GbEb
-  /* 23 */  Another, // AND_GdEd
-  /* 24 */  Immediate_Ib, // AND_ALIb
-  /* 25 */  Immediate_Iv, // AND_EAXId
-  /* 26 */  Prefix | Another, // ES:
-  /* 27 */  0, // DAA
-  /* 28 */  Another, // SUB_EbGb
-  /* 29 */  Another, // SUB_EdGd
-  /* 2A */  Another, // SUB_GbEb
-  /* 2B */  Another, // SUB_GdEd
-  /* 2C */  Immediate_Ib, // SUB_ALIb
-  /* 2D */  Immediate_Iv, // SUB_EAXId
-  /* 2E */  Prefix | Another, // CS:
-  /* 2F */  0, // DAS
-  /* 30 */  Another, // XOR_EbGb
-  /* 31 */  Another, // XOR_EdGd
-  /* 32 */  Another, // XOR_GbEb
-  /* 33 */  Another, // XOR_GdEd
-  /* 34 */  Immediate_Ib, // XOR_ALIb
-  /* 35 */  Immediate_Iv, // XOR_EAXId
-  /* 36 */  Prefix | Another, // SS:
-  /* 37 */  0, // AAA
-  /* 38 */  Another, // CMP_EbGb
-  /* 39 */  Another, // CMP_EdGd
-  /* 3A */  Another, // CMP_GbEb
-  /* 3B */  Another, // CMP_GdEd
-  /* 3C */  Immediate_Ib, // CMP_ALIb
-  /* 3D */  Immediate_Iv, // CMP_EAXId
-  /* 3E */  Prefix | Another, // DS:
-  /* 3F */  0, // AAS
-  /* 40 */  0, // INC_ERX
-  /* 41 */  0, // INC_ERX
-  /* 42 */  0, // INC_ERX
-  /* 43 */  0, // INC_ERX
-  /* 44 */  0, // INC_ERX
-  /* 45 */  0, // INC_ERX
-  /* 46 */  0, // INC_ERX
-  /* 47 */  0, // INC_ERX
-  /* 48 */  0, // DEC_ERX
-  /* 49 */  0, // DEC_ERX
-  /* 4A */  0, // DEC_ERX
-  /* 4B */  0, // DEC_ERX
-  /* 4C */  0, // DEC_ERX
-  /* 4D */  0, // DEC_ERX
-  /* 4E */  0, // DEC_ERX
-  /* 4F */  0, // DEC_ERX
-  /* 50 */  0, // PUSH_ERX
-  /* 51 */  0, // PUSH_ERX
-  /* 52 */  0, // PUSH_ERX
-  /* 53 */  0, // PUSH_ERX
-  /* 54 */  0, // PUSH_ERX
-  /* 55 */  0, // PUSH_ERX
-  /* 56 */  0, // PUSH_ERX
-  /* 57 */  0, // PUSH_ERX
-  /* 58 */  0, // POP_ERX
-  /* 59 */  0, // POP_ERX
-  /* 5A */  0, // POP_ERX
-  /* 5B */  0, // POP_ERX
-  /* 5C */  0, // POP_ERX
-  /* 5D */  0, // POP_ERX
-  /* 5E */  0, // POP_ERX
-  /* 5F */  0, // POP_ERX
-  /* 60 */  0, // PUSHAD32
-  /* 61 */  0, // POPAD32
-  /* 62 */  Another, // BOUND_GvMa
-  /* 63 */  Another, // ARPL_EwGw
-  /* 64 */  Prefix | Another, // FS:
-  /* 65 */  Prefix | Another, // GS:
-  /* 66 */  Prefix | Another, // OS:
-  /* 67 */  Prefix | Another, // AS:
-  /* 68 */  Immediate_Iv, // PUSH_Id
-  /* 69 */  Another | Immediate_Iv, // IMUL_GdEdId
-  /* 6A */  Immediate_Ib_SE, // PUSH_Id
-  /* 6B */  Another | Immediate_Ib_SE, // IMUL_GdEdId
-  /* 6C */  Repeatable, // INSB_YbDX
-  /* 6D */  Repeatable, // INSW_YvDX
-  /* 6E */  Repeatable, // OUTSB_DXXb
-  /* 6F */  Repeatable, // OUTSW_DXXv
-  /* 70 */  Immediate_BrOff8, // JCC_Jd
-  /* 71 */  Immediate_BrOff8, // JCC_Jd
-  /* 72 */  Immediate_BrOff8, // JCC_Jd
-  /* 73 */  Immediate_BrOff8, // JCC_Jd
-  /* 74 */  Immediate_BrOff8, // JCC_Jd
-  /* 75 */  Immediate_BrOff8, // JCC_Jd
-  /* 76 */  Immediate_BrOff8, // JCC_Jd
-  /* 77 */  Immediate_BrOff8, // JCC_Jd
-  /* 78 */  Immediate_BrOff8, // JCC_Jd
-  /* 79 */  Immediate_BrOff8, // JCC_Jd
-  /* 7A */  Immediate_BrOff8, // JCC_Jd
-  /* 7B */  Immediate_BrOff8, // JCC_Jd
-  /* 7C */  Immediate_BrOff8, // JCC_Jd
-  /* 7D */  Immediate_BrOff8, // JCC_Jd
-  /* 7E */  Immediate_BrOff8, // JCC_Jd
-  /* 7F */  Immediate_BrOff8, // JCC_Jd
-  /* 80 */  Another | GroupN | PutGroupIndex(G1EbIb),
-  /* 81 */  Another | GroupN | Immediate_Iv | PutGroupIndex(G1Ed),
-  /* 82 */  Another | GroupN | PutGroupIndex(G1EbIb),
-  /* 83 */  Another | GroupN | Immediate_Ib_SE | PutGroupIndex(G1Ed),
-  /* 84 */  Another, // TEST_EbGb
-  /* 85 */  Another, // TEST_EdGd
-  /* 86 */  Another, // XCHG_EbGb
-  /* 87 */  Another, // XCHG_EdGd
-  /* 88 */  Another, // MOV_EbGb
-  /* 89 */  Another, // MOV_EdGd
-  /* 8A */  Another, // MOV_GbEb
-  /* 8B */  Another, // MOV_GdEd
-  /* 8C */  Another, // MOV_EwSw
-  /* 8D */  Another, // LEA_GdM
-  /* 8E */  Another, // MOV_SwEw
-  /* 8F */  Another, // POP_Ed
-  /* 90 */  0, // NOP
-  /* 91 */  0, // XCHG_ERXEAX
-  /* 92 */  0, // XCHG_ERXEAX
-  /* 93 */  0, // XCHG_ERXEAX
-  /* 94 */  0, // XCHG_ERXEAX
-  /* 95 */  0, // XCHG_ERXEAX
-  /* 96 */  0, // XCHG_ERXEAX
-  /* 97 */  0, // XCHG_ERXEAX
-  /* 98 */  0, // CWDE
-  /* 99 */  0, // CDQ
-  /* 9A */  Immediate_IvIw, // CALL32_Ap
-  /* 9B */  0, // FWAIT
-  /* 9C */  0, // PUSHF_Fv
-  /* 9D */  0, // POPF_Fv
-  /* 9E */  0, // SAHF
-  /* 9F */  0, // LAHF
-  /* A0 */  Immediate_O, // MOV_ALOb
-  /* A1 */  Immediate_O, // MOV_EAXOd
-  /* A2 */  Immediate_O, // MOV_ObAL
-  /* A3 */  Immediate_O, // MOV_OdEAX
-  /* A4 */  Repeatable, // MOVSB_XbYb
-  /* A5 */  Repeatable, // MOVSW_XvYv
-  /* A6 */  Repeatable | RepeatableZF, // CMPSB_XbYb
-  /* A7 */  Repeatable | RepeatableZF, // CMPSW_XvYv
-  /* A8 */  Immediate_Ib, // TEST_ALIb
-  /* A9 */  Immediate_Iv, // TEST_EAXId
-  /* AA */  Repeatable, // STOSB_YbAL
-  /* AB */  Repeatable, // STOSW_YveAX
-  /* AC */  Repeatable, // LODSB_ALXb
-  /* AD */  Repeatable, // LODSW_eAXXv
-  /* AE */  Repeatable | RepeatableZF, // SCASB_ALXb
-  /* AF */  Repeatable | RepeatableZF, // SCASW_eAXXv
-  /* B0 */  Immediate_Ib, // MOV_RLIb
-  /* B1 */  Immediate_Ib, // MOV_RLIb
-  /* B2 */  Immediate_Ib, // MOV_RLIb
-  /* B3 */  Immediate_Ib, // MOV_RLIb
-  /* B4 */  Immediate_Ib, // MOV_RHIb
-  /* B5 */  Immediate_Ib, // MOV_RHIb
-  /* B6 */  Immediate_Ib, // MOV_RHIb
-  /* B7 */  Immediate_Ib, // MOV_RHIb
-  /* B8 */  Immediate_Iv, // MOV_ERXId
-  /* B9 */  Immediate_Iv, // MOV_ERXId
-  /* BA */  Immediate_Iv, // MOV_ERXId
-  /* BB */  Immediate_Iv, // MOV_ERXId
-  /* BC */  Immediate_Iv, // MOV_ERXId
-  /* BD */  Immediate_Iv, // MOV_ERXId
-  /* BE */  Immediate_Iv, // MOV_ERXId
-  /* BF */  Immediate_Iv, // MOV_ERXId
-  /* C0 */  Another | GroupN | Immediate_Ib | PutGroupIndex(G2Eb),
-  /* C1 */  Another | GroupN | Immediate_Ib | PutGroupIndex(G2Ed),
-  /* C2 */  Immediate_Iw | UCBranch, // RETnear32_Iw
-  /* C3 */  0 | UCBranch, // RETnear32
-  /* C4 */  Another, // LES_GvMp
-  /* C5 */  Another, // LDS_GvMp
-  /* C6 */  Another | Immediate_Ib, // MOV_EbIb
-  /* C7 */  Another | Immediate_Iv, // MOV_EdId
-  /* C8 */  Immediate_IwIb, // ENTER_IwIb
-  /* C9 */  0, // LEAVE
-  /* CA */  Immediate_Iw | UCBranch, // RETfar32_Iw
-  /* CB */  0 | UCBranch, // RETfar32
-  /* CC */  0, // INT3
-  /* CD */  Immediate_Ib, // INT_Ib
-  /* CE */  0, // INTO
-  /* CF */  0 | UCBranch, // IRET32
-  /* D0 */  Another | GroupN | PutGroupIndex(G2Eb),
-  /* D1 */  Another | GroupN | PutGroupIndex(G2Ed),
-  /* D2 */  Another | GroupN | PutGroupIndex(G2Eb),
-  /* D3 */  Another | GroupN | PutGroupIndex(G2Ed),
-  /* D4 */  Immediate_Ib, // AAM
-  /* D5 */  Immediate_Ib, // AAD
-  /* D6 */  0, // SALC
-  /* D7 */  0, // XLAT
-  /* D8 */  Another, // ESC0
-  /* D9 */  Another, // ESC1
-  /* DA */  Another, // ESC2
-  /* DB */  Another, // ESC3
-  /* DC */  Another, // ESC4
-  /* DD */  Another, // ESC5
-  /* DE */  Another, // ESC6
-  /* DF */  Another, // ESC7
-  /* E0 */  Immediate_BrOff8, // LOOPNE_Jb
-  /* E1 */  Immediate_BrOff8, // LOOPE_Jb
-  /* E2 */  Immediate_BrOff8, // LOOP_Jb
-  /* E3 */  Immediate_BrOff8, // JCXZ_Jb
-  /* E4 */  Immediate_Ib, // IN_ALIb
-  /* E5 */  Immediate_Ib, // IN_eAXIb
-  /* E6 */  Immediate_Ib, // OUT_IbAL
-  /* E7 */  Immediate_Ib, // OUT_IbeAX
-  /* E8 */  Immediate_BrOff32, // CALL_Ad
-  /* E9 */  Immediate_BrOff32 | UCBranch, // JMP_Jd
-  /* EA */  Immediate_IvIw | UCBranch, // JMP_Ap
-  /* EB */  Immediate_BrOff8 | UCBranch, // JMP_Jb
-  /* EC */  0, // IN_ALDX
-  /* ED */  0, // IN_eAXDX
-  /* EE */  0, // OUT_DXAL
-  /* EF */  0, // OUT_DXeAX
-  /* F0 */  Prefix | Another, // LOCK:
-  /* F1 */  0, // INT1
-  /* F2 */  Prefix | Another, // REPNE/REPNZ:
-  /* F3 */  Prefix | Another, // REP,REPE/REPZ:
-  /* F4 */  0, // HLT
-  /* F5 */  0, // CMC
-  /* F6 */  Another | GroupN | PutGroupIndex(G3Eb),
-  /* F7 */  Another | GroupN | PutGroupIndex(G3Ed),
-  /* F8 */  0, // CLC
-  /* F9 */  0, // STC
-  /* FA */  0, // CLI
-  /* FB */  0, // STI
-  /* FC */  0, // CLD
-  /* FD */  0, // STD
-  /* FE */  Another | GroupN | PutGroupIndex(G4),
-  /* FF */  Another | GroupN | PutGroupIndex(G5d),
- 
-  /* 0F 00 */  Another | GroupN | PutGroupIndex(G6),
-  /* 0F 01 */  Another | GroupN | PutGroupIndex(G7),
-  /* 0F 02 */  Another, // LAR_GvEw
-  /* 0F 03 */  Another, // LSL_GvEw
-  /* 0F 04 */  InvalidOpcode, 
-  /* 0F 05 */  0, // LOADALL
-  /* 0F 06 */  0, // CLTS
-  /* 0F 07 */  InvalidOpcode, 
-  /* 0F 08 */  0, // INVD
-  /* 0F 09 */  0, // WBINVD
-  /* 0F 0A */  InvalidOpcode, 
-  /* 0F 0B */  InvalidOpcode, 
-  /* 0F 0C */  InvalidOpcode, 
-  /* 0F 0D */  InvalidOpcode, 
-  /* 0F 0E */  InvalidOpcode, 
-  /* 0F 0F */  InvalidOpcode, 
-  /* 0F 10 */  InvalidOpcode, 
-  /* 0F 11 */  InvalidOpcode, 
-  /* 0F 12 */  InvalidOpcode, 
-  /* 0F 13 */  InvalidOpcode, 
-  /* 0F 14 */  InvalidOpcode, 
-  /* 0F 15 */  InvalidOpcode, 
-  /* 0F 16 */  InvalidOpcode, 
-  /* 0F 17 */  InvalidOpcode, 
-  /* 0F 18 */  InvalidOpcode, 
-  /* 0F 19 */  InvalidOpcode, 
-  /* 0F 1A */  InvalidOpcode, 
-  /* 0F 1B */  InvalidOpcode, 
-  /* 0F 1C */  InvalidOpcode, 
-  /* 0F 1D */  InvalidOpcode, 
-  /* 0F 1E */  InvalidOpcode, 
-  /* 0F 1F */  InvalidOpcode, 
-  /* 0F 20 */  Another, // MOV_RdCd
-  /* 0F 21 */  Another, // MOV_RdDd
-  /* 0F 22 */  Another, // MOV_CdRd
-  /* 0F 23 */  Another, // MOV_DdRd
-  /* 0F 24 */  Another, // MOV_RdTd
-  /* 0F 25 */  InvalidOpcode, 
-  /* 0F 26 */  Another, // MOV_TdRd
-  /* 0F 27 */  InvalidOpcode, 
-  /* 0F 28 */  InvalidOpcode, 
-  /* 0F 29 */  InvalidOpcode, 
-  /* 0F 2A */  InvalidOpcode, 
-  /* 0F 2B */  InvalidOpcode, 
-  /* 0F 2C */  InvalidOpcode, 
-  /* 0F 2D */  InvalidOpcode, 
-  /* 0F 2E */  InvalidOpcode, 
-  /* 0F 2F */  InvalidOpcode, 
-  /* 0F 30 */  0, // WRMSR
-  /* 0F 31 */  0, // RDTSC
-  /* 0F 32 */  0, // RDMSR
-  /* 0F 33 */  InvalidOpcode, 
-  /* 0F 34 */  InvalidOpcode, 
-  /* 0F 35 */  InvalidOpcode, 
-  /* 0F 36 */  InvalidOpcode, 
-  /* 0F 37 */  InvalidOpcode, 
-  /* 0F 38 */  InvalidOpcode, 
-  /* 0F 39 */  InvalidOpcode, 
-  /* 0F 3A */  InvalidOpcode, 
-  /* 0F 3B */  InvalidOpcode, 
-  /* 0F 3C */  InvalidOpcode, 
-  /* 0F 3D */  InvalidOpcode, 
-  /* 0F 3E */  InvalidOpcode, 
-  /* 0F 3F */  InvalidOpcode, 
-  /* 0F 40 */  Another, // CMOV_GdEd
-  /* 0F 41 */  Another, // CMOV_GdEd
-  /* 0F 42 */  Another, // CMOV_GdEd
-  /* 0F 43 */  Another, // CMOV_GdEd
-  /* 0F 44 */  Another, // CMOV_GdEd
-  /* 0F 45 */  Another, // CMOV_GdEd
-  /* 0F 46 */  Another, // CMOV_GdEd
-  /* 0F 47 */  Another, // CMOV_GdEd
-  /* 0F 48 */  Another, // CMOV_GdEd
-  /* 0F 49 */  Another, // CMOV_GdEd
-  /* 0F 4A */  Another, // CMOV_GdEd
-  /* 0F 4B */  Another, // CMOV_GdEd
-  /* 0F 4C */  Another, // CMOV_GdEd
-  /* 0F 4D */  Another, // CMOV_GdEd
-  /* 0F 4E */  Another, // CMOV_GdEd
-  /* 0F 4F */  Another, // CMOV_GdEd
-  /* 0F 50 */  InvalidOpcode, 
-  /* 0F 51 */  InvalidOpcode, 
-  /* 0F 52 */  InvalidOpcode, 
-  /* 0F 53 */  InvalidOpcode, 
-  /* 0F 54 */  InvalidOpcode, 
-  /* 0F 55 */  InvalidOpcode, 
-  /* 0F 56 */  InvalidOpcode, 
-  /* 0F 57 */  InvalidOpcode, 
-  /* 0F 58 */  InvalidOpcode, 
-  /* 0F 59 */  InvalidOpcode, 
-  /* 0F 5A */  InvalidOpcode, 
-  /* 0F 5B */  InvalidOpcode, 
-  /* 0F 5C */  InvalidOpcode, 
-  /* 0F 5D */  InvalidOpcode, 
-  /* 0F 5E */  InvalidOpcode, 
-  /* 0F 5F */  InvalidOpcode, 
-  /* 0F 60 */  InvalidOpcode, 
-  /* 0F 61 */  InvalidOpcode, 
-  /* 0F 62 */  InvalidOpcode, 
-  /* 0F 63 */  InvalidOpcode, 
-  /* 0F 64 */  InvalidOpcode, 
-  /* 0F 65 */  InvalidOpcode, 
-  /* 0F 66 */  InvalidOpcode, 
-  /* 0F 67 */  InvalidOpcode, 
-  /* 0F 68 */  InvalidOpcode, 
-  /* 0F 69 */  InvalidOpcode, 
-  /* 0F 6A */  InvalidOpcode, 
-  /* 0F 6B */  InvalidOpcode, 
-  /* 0F 6C */  InvalidOpcode, 
-  /* 0F 6D */  InvalidOpcode, 
-  /* 0F 6E */  InvalidOpcode, 
-  /* 0F 6F */  InvalidOpcode, 
-  /* 0F 70 */  InvalidOpcode, 
-  /* 0F 71 */  InvalidOpcode, 
-  /* 0F 72 */  InvalidOpcode, 
-  /* 0F 73 */  InvalidOpcode, 
-  /* 0F 74 */  InvalidOpcode, 
-  /* 0F 75 */  InvalidOpcode, 
-  /* 0F 76 */  InvalidOpcode, 
-  /* 0F 77 */  InvalidOpcode, 
-  /* 0F 78 */  InvalidOpcode, 
-  /* 0F 79 */  InvalidOpcode, 
-  /* 0F 7A */  InvalidOpcode, 
-  /* 0F 7B */  InvalidOpcode, 
-  /* 0F 7C */  InvalidOpcode, 
-  /* 0F 7D */  InvalidOpcode, 
-  /* 0F 7E */  InvalidOpcode, 
-  /* 0F 7F */  InvalidOpcode, 
-  /* 0F 80 */  Immediate_BrOff32, // JCC_Jd
-  /* 0F 81 */  Immediate_BrOff32, // JCC_Jd
-  /* 0F 82 */  Immediate_BrOff32, // JCC_Jd
-  /* 0F 83 */  Immediate_BrOff32, // JCC_Jd
-  /* 0F 84 */  Immediate_BrOff32, // JCC_Jd
-  /* 0F 85 */  Immediate_BrOff32, // JCC_Jd
-  /* 0F 86 */  Immediate_BrOff32, // JCC_Jd
-  /* 0F 87 */  Immediate_BrOff32, // JCC_Jd
-  /* 0F 88 */  Immediate_BrOff32, // JCC_Jd
-  /* 0F 89 */  Immediate_BrOff32, // JCC_Jd
-  /* 0F 8A */  Immediate_BrOff32, // JCC_Jd
-  /* 0F 8B */  Immediate_BrOff32, // JCC_Jd
-  /* 0F 8C */  Immediate_BrOff32, // JCC_Jd
-  /* 0F 8D */  Immediate_BrOff32, // JCC_Jd
-  /* 0F 8E */  Immediate_BrOff32, // JCC_Jd
-  /* 0F 8F */  Immediate_BrOff32, // JCC_Jd
-  /* 0F 90 */  Another, // SETO_Eb
-  /* 0F 91 */  Another, // SETNO_Eb
-  /* 0F 92 */  Another, // SETB_Eb
-  /* 0F 93 */  Another, // SETNB_Eb
-  /* 0F 94 */  Another, // SETZ_Eb
-  /* 0F 95 */  Another, // SETNZ_Eb
-  /* 0F 96 */  Another, // SETBE_Eb
-  /* 0F 97 */  Another, // SETNBE_Eb
-  /* 0F 98 */  Another, // SETS_Eb
-  /* 0F 99 */  Another, // SETNS_Eb
-  /* 0F 9A */  Another, // SETP_Eb
-  /* 0F 9B */  Another, // SETNP_Eb
-  /* 0F 9C */  Another, // SETL_Eb
-  /* 0F 9D */  Another, // SETNL_Eb
-  /* 0F 9E */  Another, // SETLE_Eb
-  /* 0F 9F */  Another, // SETNLE_Eb
-  /* 0F A0 */  0, // PUSH_FS
-  /* 0F A1 */  0, // POP_FS
-  /* 0F A2 */  0, // CPUID
-  /* 0F A3 */  Another, // BT_EvGv
-  /* 0F A4 */  Another | Immediate_Ib, // SHLD_EdGd
-  /* 0F A5 */  Another, // SHLD_EdGd
-  /* 0F A6 */  0, // CMPXCHG_XBTS
-  /* 0F A7 */  0, // CMPXCHG_IBTS
-  /* 0F A8 */  0, // PUSH_GS
-  /* 0F A9 */  0, // POP_GS
-  /* 0F AA */  0, // RSM
-  /* 0F AB */  Another, // BTS_EvGv
-  /* 0F AC */  Another | Immediate_Ib, // SHRD_EdGd
-  /* 0F AD */  Another, // SHRD_EdGd
-  /* 0F AE */  InvalidOpcode, 
-  /* 0F AF */  Another, // IMUL_GdEd
-  /* 0F B0 */  Another, // CMPXCHG_EbGb
-  /* 0F B1 */  Another, // CMPXCHG_EdGd
-  /* 0F B2 */  Another, // LSS_GvMp
-  /* 0F B3 */  Another, // BTR_EvGv
-  /* 0F B4 */  Another, // LFS_GvMp
-  /* 0F B5 */  Another, // LGS_GvMp
-  /* 0F B6 */  Another, // MOVZX_GdEb
-  /* 0F B7 */  Another, // MOVZX_GdEw
-  /* 0F B8 */  InvalidOpcode, 
-  /* 0F B9 */  InvalidOpcode, 
-  /* 0F BA */  Another | GroupN | PutGroupIndex(G8EvIb),
-  /* 0F BB */  Another, // BTC_EvGv
-  /* 0F BC */  Another, // BSF_GvEv
-  /* 0F BD */  Another, // BSR_GvEv
-  /* 0F BE */  Another, // MOVSX_GdEb
-  /* 0F BF */  Another, // MOVSX_GdEw
-  /* 0F C0 */  Another, // XADD_EbGb
-  /* 0F C1 */  Another, // XADD_EdGd
-  /* 0F C2 */  InvalidOpcode, 
-  /* 0F C3 */  InvalidOpcode, 
-  /* 0F C4 */  InvalidOpcode, 
-  /* 0F C5 */  InvalidOpcode, 
-  /* 0F C6 */  InvalidOpcode, 
-  /* 0F C7 */  Another | GroupN | PutGroupIndex(G9),
-  /* 0F C8 */  0, // BSWAP_EAX
-  /* 0F C9 */  0, // BSWAP_ECX
-  /* 0F CA */  0, // BSWAP_EDX
-  /* 0F CB */  0, // BSWAP_EBX
-  /* 0F CC */  0, // BSWAP_ESP
-  /* 0F CD */  0, // BSWAP_EBP
-  /* 0F CE */  0, // BSWAP_ESI
-  /* 0F CF */  0, // BSWAP_EDI
-  /* 0F D0 */  InvalidOpcode, 
-  /* 0F D1 */  InvalidOpcode, 
-  /* 0F D2 */  InvalidOpcode, 
-  /* 0F D3 */  InvalidOpcode, 
-  /* 0F D4 */  InvalidOpcode, 
-  /* 0F D5 */  InvalidOpcode, 
-  /* 0F D6 */  InvalidOpcode, 
-  /* 0F D7 */  InvalidOpcode, 
-  /* 0F D8 */  InvalidOpcode, 
-  /* 0F D9 */  InvalidOpcode, 
-  /* 0F DA */  InvalidOpcode, 
-  /* 0F DB */  InvalidOpcode, 
-  /* 0F DC */  InvalidOpcode, 
-  /* 0F DD */  InvalidOpcode, 
-  /* 0F DE */  InvalidOpcode, 
-  /* 0F DF */  InvalidOpcode, 
-  /* 0F E0 */  InvalidOpcode, 
-  /* 0F E1 */  InvalidOpcode, 
-  /* 0F E2 */  InvalidOpcode, 
-  /* 0F E3 */  InvalidOpcode, 
-  /* 0F E4 */  InvalidOpcode, 
-  /* 0F E5 */  InvalidOpcode, 
-  /* 0F E6 */  InvalidOpcode, 
-  /* 0F E7 */  InvalidOpcode, 
-  /* 0F E8 */  InvalidOpcode, 
-  /* 0F E9 */  InvalidOpcode, 
-  /* 0F EA */  InvalidOpcode, 
-  /* 0F EB */  InvalidOpcode, 
-  /* 0F EC */  InvalidOpcode, 
-  /* 0F ED */  InvalidOpcode, 
-  /* 0F EE */  InvalidOpcode, 
-  /* 0F EF */  InvalidOpcode, 
-  /* 0F F0 */  InvalidOpcode, 
-  /* 0F F1 */  InvalidOpcode, 
-  /* 0F F2 */  InvalidOpcode, 
-  /* 0F F3 */  InvalidOpcode, 
-  /* 0F F4 */  InvalidOpcode, 
-  /* 0F F5 */  InvalidOpcode, 
-  /* 0F F6 */  InvalidOpcode, 
-  /* 0F F7 */  InvalidOpcode, 
-  /* 0F F8 */  InvalidOpcode, 
-  /* 0F F9 */  InvalidOpcode, 
-  /* 0F FA */  InvalidOpcode, 
-  /* 0F FB */  InvalidOpcode, 
-  /* 0F FC */  InvalidOpcode, 
-  /* 0F FD */  InvalidOpcode, 
-  /* 0F FE */  InvalidOpcode, 
-  /* 0F FF */  InvalidOpcode, 
-  };
-
-
-
-  unsigned
-fetchDecode(Bit8u *iptr, instruction_t *instruction,
-                      unsigned remain, Boolean is_32)
+
+/*
+ *  the default segment to use for a one-byte modrm with mod==01b
+ *  and rm==i
+ */
+
+static const unsigned sreg_mod01_rm32[8] =
 {
-  // remain must be at least 1
+    SEG_REG_DS,
+    SEG_REG_DS,
+    SEG_REG_DS,
+    SEG_REG_DS,
+    SEG_REG_NULL,  /* this entry should never be accessed (escape to 2-byte) */
+    SEG_REG_SS,
+    SEG_REG_DS,
+    SEG_REG_DS
+};
 
-  unsigned b1, b2, ilen=1, attr;
-  unsigned imm_mode, offset;
-  unsigned rm;
 
-  instruction->os_32 = instruction->as_32 = is_32;
-//  instruction->ResolveModrm = NULL;
-  instruction->seg = SEG_REG_NULL;
-  instruction->rep_used = 0;
+/*
+ *  the default segment to use for a one-byte modrm with mod==10b
+ *  and rm==i
+ */
+
+static const unsigned sreg_mod10_rm32[8] =
+{
+    SEG_REG_DS,
+    SEG_REG_DS,
+    SEG_REG_DS,
+    SEG_REG_DS,
+    SEG_REG_NULL,  /* this entry should never be accessed (escape to 2-byte) */
+    SEG_REG_SS,
+    SEG_REG_DS,
+    SEG_REG_DS
+};
 
 
-fetch_b1:
-  b1 = *iptr++;
+/*
+ *  the default segment to use for a two-byte modrm with mod==00b
+ *  and base==i
+ */
+
+static const unsigned sreg_mod0_base32[8] =
+{
+    SEG_REG_DS,
+    SEG_REG_DS,
+    SEG_REG_DS,
+    SEG_REG_DS,
+    SEG_REG_SS,
+    SEG_REG_DS,
+    SEG_REG_DS,
+    SEG_REG_DS
+};
+
+
+/*
+ *  the default segment to use for a two-byte modrm with
+ *  mod==01b or mod==10b and base==i
+ */
+
+static const unsigned sreg_mod1or2_base32[8] =
+{
+    SEG_REG_DS,
+    SEG_REG_DS,
+    SEG_REG_DS,
+    SEG_REG_DS,
+    SEG_REG_SS,
+    SEG_REG_SS,
+    SEG_REG_DS,
+    SEG_REG_DS
+};
 
-another_byte:
-  offset = instruction->os_32 << 9; // * 512
-  instruction->attr = attr = OpcodeInfo[b1+offset];
-
-  if (attr & Another) {
-    if (attr & Prefix) {
-      switch (b1) {
-        case 0x66: // OpSize
-          instruction->os_32 = !is_32;
-          if (ilen < remain) {
-            ilen++;
-            goto fetch_b1;
-            }
-          return(0);
-
-        case 0x67: // AddrSize
-          instruction->as_32 = !is_32;
-          if (ilen < remain) {
-            ilen++;
-            goto fetch_b1;
-            }
-          return(0);
-
-        case 0xf2: // REPNE/REPNZ
-        case 0xf3: // REP/REPE/REPZ
-          instruction->rep_used = b1;
-          if (ilen < remain) {
-            ilen++;
-            goto fetch_b1;
-            }
-          return(0);
-          break;
-
-        case 0x2e: // CS:
-          instruction->seg = SEG_REG_CS;
-          ilen++; goto fetch_b1;
-          break;
-        case 0x26: // ES:
-          instruction->seg = SEG_REG_ES;
-          ilen++; goto fetch_b1;
-          break;
-        case 0x36: // SS:
-          instruction->seg = SEG_REG_SS;
-          ilen++; goto fetch_b1;
-          break;
-        case 0x3e: // DS:
-          instruction->seg = SEG_REG_DS;
-          ilen++; goto fetch_b1;
-          break;
-        case 0x64: // FS:
-          instruction->seg = SEG_REG_FS;
-          ilen++; goto fetch_b1;
-          break;
-        case 0x65: // GS:
-          instruction->seg = SEG_REG_GS;
-          ilen++; goto fetch_b1;
-          break;
-        case 0xf0: // LOCK:
-          ilen++; goto fetch_b1;
-          break;
-
-        default:
-          return(0);
-//panic("fetch_decode: prefix default = 0x%02x\n", b1);
-        }
-      }
-    // opcode requires another byte
-    if (ilen < remain) {
-      ilen++;
-      b2 = *iptr++;
-      if (b1 == 0x0f) {
-        // 2-byte prefix
-        b1 = 0x100 | b2;
-        goto another_byte;
-        }
-      }
-    else
-      return(0);
 
-    // Parse mod-nnn-rm and related bytes
-    instruction->modrm = b2;
-    rm =
-    instruction->rm    = b2 & 0x07;
-    instruction->mod   = b2 & 0xc0; // leave unshifted
-    instruction->nnn   = (b2 >> 3) & 0x07;
-    if (instruction->mod == 0xc0) { // mod == 11b
-      goto modrm_done;
-      }
-    if (instruction->as_32) {
-      // 32-bit addressing modes; note that mod==11b handled above
-      if (rm != 4) { // no s-i-b byte
-        if (instruction->mod == 0x00) { // mod == 00b
-//          instruction->ResolveModrm = BxResolve32Mod0[rm];
-          if (NULL_SEG_REG(instruction->seg))
-            instruction->seg = SEG_REG_DS;
-          if (rm == 5) {
-            if ((ilen+3) < remain) {
-              Bit32u imm32u;
-              imm32u = *iptr++;
-              imm32u |= (*iptr++) << 8;
-              imm32u |= (*iptr++) << 16;
-              imm32u |= (*iptr++) << 24;
-              instruction->rm_addr = imm32u;
-              ilen += 4;
-              goto modrm_done;
-              }
-            else {
-              return(0);
-              }
-            }
-          // mod==00b, rm!=4, rm!=5
-          goto modrm_done;
-          }
-        if (instruction->mod == 0x40) { // mod == 01b
-//          instruction->ResolveModrm = BxResolve32Mod1or2[rm];
-          if (NULL_SEG_REG(instruction->seg))
-            instruction->seg = sreg_mod01_rm32[rm];
-get_8bit_displ:
-          if (ilen < remain) {
-            // 8 sign extended to 32
-            instruction->displ32u = (Bit8s) *iptr++;
-            ilen++;
-            goto modrm_done;
-            }
-          else {
-            return(0);
-            }
-          }
-        // (mod == 0x80) mod == 10b
-//        instruction->ResolveModrm = BxResolve32Mod1or2[rm];
-        if (NULL_SEG_REG(instruction->seg))
-          instruction->seg = sreg_mod10_rm32[rm];
-get_32bit_displ:
-        if ((ilen+3) < remain) {
-          Bit32u imm32u;
-          imm32u = *iptr++;
-          imm32u |= (*iptr++) << 8;
-          imm32u |= (*iptr++) << 16;
-          imm32u |= (*iptr++) << 24;
-          instruction->displ32u = imm32u;
-          ilen += 4;
-          goto modrm_done;
-          }
-        else {
-          return(0);
-          }
-        }
-      else { // mod!=11b, rm==4, s-i-b byte follows
-        unsigned sib, base;
-        if (ilen < remain) {
-          sib = *iptr++;
-          ilen++;
-          }
-        else {
-          return(0);
-          }
-        instruction->sib   = sib;
-        base =
-        instruction->base  = sib & 0x07; sib >>= 3;
-        instruction->index = sib & 0x07; sib >>= 3;
-        instruction->scale = sib;
-        if (instruction->mod == 0x00) { // mod==00b, rm==4
-//          instruction->ResolveModrm = BxResolve32Mod0Base[base];
-          if (NULL_SEG_REG(instruction->seg))
-            instruction->seg = sreg_mod0_base32[base];
-          if (instruction->base == 0x05) {
-            goto get_32bit_displ;
-            }
-          // mod==00b, rm==4, base!=5
-          goto modrm_done;
-          }
-        if (instruction->mod == 0x40) { // mod==01b, rm==4
-//          instruction->ResolveModrm = BxResolve32Mod1or2Base[base];
-          if (NULL_SEG_REG(instruction->seg))
-            instruction->seg = sreg_mod1or2_base32[base];
-          goto get_8bit_displ;
-          }
-        // (instruction->mod == 0x80),  mod==10b, rm==4
-//        instruction->ResolveModrm = BxResolve32Mod1or2Base[base];
-        if (NULL_SEG_REG(instruction->seg))
-          instruction->seg = sreg_mod1or2_base32[base];
-        goto get_32bit_displ;
-        }
-      }
-    else {
-      // 16-bit addressing modes, mod==11b handled above
-      if (instruction->mod == 0x40) { // mod == 01b
-//        instruction->ResolveModrm = BxResolve16Mod1or2[rm];
-        if (NULL_SEG_REG(instruction->seg))
-          instruction->seg = sreg_mod01_rm16[rm];
-        if (ilen < remain) {
-          // 8 sign extended to 16
-          instruction->displ16u = (Bit8s) *iptr++;
-          ilen++;
-          goto modrm_done;
-          }
-        else {
-          return(0);
-          }
-        }
-      if (instruction->mod == 0x80) { // mod == 10b
-//        instruction->ResolveModrm = BxResolve16Mod1or2[rm];
-        if (NULL_SEG_REG(instruction->seg))
-          instruction->seg = sreg_mod10_rm16[rm];
-        if ((ilen+1) < remain) {
-          Bit16u displ16u;
-          displ16u = *iptr++;
-          displ16u |= (*iptr++) << 8;
-          instruction->displ16u = displ16u;
-          ilen += 2;
-          goto modrm_done;
-          }
-        else {
-          return(0);
-          }
-        }
-      // mod must be 00b at this point
-//      instruction->ResolveModrm = BxResolve16Mod0[rm];
-      if (NULL_SEG_REG(instruction->seg))
-        instruction->seg = sreg_mod00_rm16[rm];
-      if (rm == 0x06) {
-        if ((ilen+1) < remain) {
-          Bit16u displ16u;
-          displ16u = *iptr++;
-          displ16u |= (*iptr++) << 8;
-          instruction->rm_addr = displ16u;
-          ilen += 2;
-          goto modrm_done;
-          }
-        else {
-          return(0);
-          }
-        }
-      // mod=00b rm!=6
-      }
-
-modrm_done:
-    if (attr & GroupN) {
-      // There may be additional attributes in the individual entry
-      // for a particular group.  Combine with those.
-      attr |= groupNattr[GetGroupIndex(attr)][instruction->nnn];
-      instruction->attr = attr;
-      }
-    else {
-      }
+static Bit16u groupNattr[NumGroups][8] =
+{
+/* G1EbIb */
+    {
+	/* 0 */ Immediate_Ib,	/* ADD_EbIb   */
+	/* 1 */ Immediate_Ib,	/* OR_EbIb    */
+	/* 2 */ Immediate_Ib,	/* ADC_EbIb   */
+	/* 3 */ Immediate_Ib,	/* SBB_EbIb   */
+	/* 4 */ Immediate_Ib,	/* AND_EbIb   */
+	/* 5 */ Immediate_Ib,	/* SUB_EbIb   */
+	/* 6 */ Immediate_Ib,	/* XOR_EbIb   */
+	/* 7 */ Immediate_Ib,	/* CMP_EbIb   */
+    },
+
+/* G1Ew (attributes defined in main area) */
+    {
+	/* 0 */ 0,		/* ADD_EwIw   */
+	/* 1 */ 0,		/* OR_EwIw    */
+	/* 2 */ 0,		/* ADC_EwIw   */
+	/* 3 */ 0,		/* SBB_EwIw   */
+	/* 4 */ 0,		/* AND_EwIw   */
+	/* 5 */ 0,		/* SUB_EwIw   */
+	/* 6 */ 0,		/* XOR_EwIw   */
+	/* 7 */ 0,		/* CMP_EwIw   */
+    },
+
+/* G1Ed (attributes defined in main area) */
+    {
+	/* 0 */ 0,		/* ADD_EdId   */
+	/* 1 */ 0,		/* OR_EdId    */
+	/* 2 */ 0,		/* ADC_EdId   */
+	/* 3 */ 0,		/* SBB_EdId   */
+	/* 4 */ 0,		/* AND_EdId   */
+	/* 5 */ 0,		/* SUB_EdId   */
+	/* 6 */ 0,		/* XOR_EdId   */
+	/* 7 */ 0,		/* CMP_EdId   */
+    },
+
+/* G2Eb (attributes defined in main area) */
+    {
+	/* 0 */ 0,		/* ROL_Eb     */
+	/* 1 */ 0,		/* ROR_Eb     */
+	/* 2 */ 0,		/* RCL_Eb     */
+	/* 3 */ 0,		/* RCR_Eb     */
+	/* 4 */ 0,		/* SHL_Eb     */
+	/* 5 */ 0,		/* SHR_Eb     */
+	/* 6 */ 0,		/* SHL_Eb     */
+	/* 7 */ 0,		/* SAR_Eb     */
+    },
+
+/* G2Ew (attributes defined in main area) */
+    {
+	/* 0 */ 0,		/* ROL_Ew     */
+	/* 1 */ 0,		/* ROR_Ew     */
+	/* 2 */ 0,		/* RCL_Ew     */
+	/* 3 */ 0,		/* RCR_Ew     */
+	/* 4 */ 0,		/* SHL_Ew     */
+	/* 5 */ 0,		/* SHR_Ew     */
+	/* 6 */ 0,		/* SHL_Ew     */
+	/* 7 */ 0,		/* SAR_Ew     */
+    },
+
+/* G2Ed (attributes defined in main area) */
+    {
+	/* 0 */ 0,		/* ROL_Ed     */
+	/* 1 */ 0,		/* ROR_Ed     */
+	/* 2 */ 0,		/* RCL_Ed     */
+	/* 3 */ 0,		/* RCR_Ed     */
+	/* 4 */ 0,		/* SHL_Ed     */
+	/* 5 */ 0,		/* SHR_Ed     */
+	/* 6 */ 0,		/* SHL_Ed     */
+	/* 7 */ 0,		/* SAR_Ed     */
+    },
+
+/* G3Eb */
+    {
+	/* 0 */ Immediate_Ib,	/* TEST_EbIb  */
+	/* 1 */ Immediate_Ib,	/* TEST_EbIb  */
+	/* 2 */ 0,		/* NOT_Eb     */
+	/* 3 */ 0,		/* NEG_Eb     */
+	/* 4 */ 0,		/* MUL_ALEb   */
+	/* 5 */ 0,		/* IMUL_ALEb  */
+	/* 6 */ 0,		/* DIV_ALEb   */
+	/* 7 */ 0,		/* IDIV_ALEb  */
+    },
+
+/* G3Ew */
+    {
+	/* 0 */ Immediate_Iw,	/* TEST_EwIw  */
+	/* 1 */ Immediate_Iw,	/* TEST_EwIw  */
+	/* 2 */ 0,		/* NOT_Ew     */
+	/* 3 */ 0,		/* NEG_Ew     */
+	/* 4 */ 0,		/* MUL_AXEw   */
+	/* 5 */ 0,		/* IMUL_AXEw  */
+	/* 6 */ 0,		/* DIV_AXEw   */
+	/* 7 */ 0,		/* IDIV_AXEw  */
+    },
+
+/* G3Ed */
+    {
+	/* 0 */ Immediate_Iv,	/* TEST_EdId  */
+	/* 1 */ Immediate_Iv,	/* TEST_EdId  */
+	/* 2 */ 0,		/* NOT_Ed     */
+	/* 3 */ 0,		/* NEG_Ed     */
+	/* 4 */ 0,		/* MUL_EAXEd  */
+	/* 5 */ 0,		/* IMUL_EAXEd */
+	/* 6 */ 0,		/* DIV_EAXEd  */
+	/* 7 */ 0,		/* IDIV_EAXEd */
+    },
+
+/* G4 */
+    {
+	/* 0 */ 0,		/* INC_Eb     */
+	/* 1 */ 0,		/* DEC_Eb     */
+	/* 2 */ InvalidOpcode,
+	/* 3 */ InvalidOpcode,
+	/* 4 */ InvalidOpcode,
+	/* 5 */ InvalidOpcode,
+	/* 6 */ InvalidOpcode,
+	/* 7 */ InvalidOpcode,
+    },
+
+/* G5w (attributes defined in main area) */
+    {
+	/* 0 */ 0,		/* INC_Ew     */
+	/* 1 */ 0,		/* DEC_Ew     */
+	/* 2 */ 0,		/* CALL_Ew    */
+	/* 3 */ 0,		/* CALL16_Ep  */
+	/* 4 */ 0 | UCBranch,	/* JMP_Ew     */
+	/* 5 */ 0 | UCBranch,	/* JMP16_Ep   */
+	/* 6 */ 0,		/* PUSH_Ew    */
+	/* 7 */ InvalidOpcode,
+    },
+
+/* G5d (attributes defined in main area) */
+    {
+	/* 0 */ 0,		/* INC_Ed     */
+	/* 1 */ 0,		/* DEC_Ed     */
+	/* 2 */ 0,		/* CALL_Ed    */
+	/* 3 */ 0,		/* CALL32_Ep  */
+	/* 4 */ 0 | UCBranch,	/* JMP_Ed     */
+	/* 5 */ 0 | UCBranch,	/* JMP32_Ep   */
+	/* 6 */ 0,		/* PUSH_Ed    */
+	/* 7 */ InvalidOpcode,
+    },
+
+/* G6 (attributes defined in main area) */
+    {
+	/* 0 */ 0,		/* SLDT_Ew    */
+	/* 1 */ 0,		/* STR_Ew     */
+	/* 2 */ 0,		/* LLDT_Ew    */
+	/* 3 */ 0,		/* LTR_Ew     */
+	/* 4 */ 0,		/* VERR_Ew    */
+	/* 5 */ 0,		/* VERW_Ew    */
+	/* 6 */ InvalidOpcode,
+	/* 7 */ InvalidOpcode,
+    },
+
+/* G7 */
+    {
+	/* 0 */ 0,		/* SGDT_Ms    */
+	/* 1 */ 0,		/* SIDT_Ms    */
+	/* 2 */ 0,		/* LGDT_Ms    */
+	/* 3 */ 0,		/* LIDT_Ms    */
+	/* 4 */ 0,		/* SMSW_Ew    */
+	/* 5 */ InvalidOpcode,
+	/* 6 */ 0,		/* LMSW_Ew    */
+	/* 7 */ 0,		/* INVLPG     */
+    },
+
+/* G8EvIb */
+    {
+	/* 0 */ InvalidOpcode,
+	/* 1 */ InvalidOpcode,
+	/* 2 */ InvalidOpcode,
+	/* 3 */ InvalidOpcode,
+	/* 4 */ Immediate_Ib,	/* BT_EvIb    */
+	/* 5 */ Immediate_Ib,	/* BTS_EvIb   */
+	/* 6 */ Immediate_Ib,	/* BTR_EvIb   */
+	/* 7 */ Immediate_Ib,	/* BTC_EvIb   */
+    },
+
+/* G9 */
+    {
+	/* 0 */ InvalidOpcode,
+	/* 1 */ 0,		/* CMPXCHG8B  */
+	/* 2 */ InvalidOpcode,
+	/* 3 */ InvalidOpcode,
+	/* 4 */ InvalidOpcode,
+	/* 5 */ InvalidOpcode,
+	/* 6 */ InvalidOpcode,
+	/* 7 */ InvalidOpcode,
+    },
+};
+
+
+/*
+ *  512 entries for 16bit mode
+ *  512 entries for 32bit mode
+ */
+
+static Bit16u OpcodeInfo[512 * 2] =
+{
+/* 512 entries for 16bit mode */
+    /* 00 */ Another,			/* ADD_EbGb		*/
+    /* 01 */ Another,			/* ADD_EwGw		*/
+    /* 02 */ Another,			/* ADD_GbEb		*/
+    /* 03 */ Another,			/* ADD_GwEw		*/
+    /* 04 */ Immediate_Ib,		/* ADD_ALIb		*/
+    /* 05 */ Immediate_Iv,		/* ADD_AXIw		*/
+    /* 06 */ 0,				/* PUSH_ES		*/
+    /* 07 */ 0,				/* POP_ES		*/
+    /* 08 */ Another,			/* OR_EbGb		*/
+    /* 09 */ Another,			/* OR_EwGw		*/
+    /* 0A */ Another,			/* OR_GbEb		*/
+    /* 0B */ Another,			/* OR_GwEw		*/
+    /* 0C */ Immediate_Ib,		/* OR_ALIb		*/
+    /* 0D */ Immediate_Iv,		/* OR_AXIw		*/
+    /* 0E */ 0,				/* PUSH_CS		*/
+    /* 0F */ Another,			/* 2-byte escape	*/
+    /* 10 */ Another,			/* ADC_EbGb		*/
+    /* 11 */ Another,			/* ADC_EwGw		*/
+    /* 12 */ Another,			/* ADC_GbEb		*/
+    /* 13 */ Another,			/* ADC_GwEw		*/
+    /* 14 */ Immediate_Ib,		/* ADC_ALIb		*/
+    /* 15 */ Immediate_Iv,		/* ADC_AXIw		*/
+    /* 16 */ 0,				/* PUSH_SS		*/
+    /* 17 */ 0,				/* POP_SS		*/
+    /* 18 */ Another,			/* SBB_EbGb		*/
+    /* 19 */ Another,			/* SBB_EwGw		*/
+    /* 1A */ Another,			/* SBB_GbEb		*/
+    /* 1B */ Another,			/* SBB_GwEw		*/
+    /* 1C */ Immediate_Ib,		/* SBB_ALIb		*/
+    /* 1D */ Immediate_Iv,		/* SBB_AXIw		*/
+    /* 1E */ 0,				/* PUSH_DS		*/
+    /* 1F */ 0,				/* POP_DS		*/
+    /* 20 */ Another,			/* AND_EbGb		*/
+    /* 21 */ Another,			/* AND_EwGw		*/
+    /* 22 */ Another,			/* AND_GbEb		*/
+    /* 23 */ Another,			/* AND_GwEw		*/
+    /* 24 */ Immediate_Ib,		/* AND_ALIb		*/
+    /* 25 */ Immediate_Iv,		/* AND_AXIw		*/
+    /* 26 */ Prefix | Another,		/* ES:			*/
+    /* 27 */ 0,				/* DAA			*/
+    /* 28 */ Another,			/* SUB_EbGb		*/
+    /* 29 */ Another,			/* SUB_EwGw		*/
+    /* 2A */ Another,			/* SUB_GbEb		*/
+    /* 2B */ Another,			/* SUB_GwEw		*/
+    /* 2C */ Immediate_Ib,		/* SUB_ALIb		*/
+    /* 2D */ Immediate_Iv,		/* SUB_AXIw		*/
+    /* 2E */ Prefix | Another,		/* CS:			*/
+    /* 2F */ 0,				/* DAS			*/
+    /* 30 */ Another,			/* XOR_EbGb		*/
+    /* 31 */ Another,			/* XOR_EwGw		*/
+    /* 32 */ Another,			/* XOR_GbEb		*/
+    /* 33 */ Another,			/* XOR_GwEw		*/
+    /* 34 */ Immediate_Ib,		/* XOR_ALIb		*/
+    /* 35 */ Immediate_Iv,		/* XOR_AXIw		*/
+    /* 36 */ Prefix | Another,		/* SS:			*/
+    /* 37 */ 0,				/* AAA			*/
+    /* 38 */ Another,			/* CMP_EbGb		*/
+    /* 39 */ Another,			/* CMP_EwGw		*/
+    /* 3A */ Another,			/* CMP_GbEb		*/
+    /* 3B */ Another,			/* CMP_GwEw		*/
+    /* 3C */ Immediate_Ib,		/* CMP_ALIb		*/
+    /* 3D */ Immediate_Iv,		/* CMP_AXIw		*/
+    /* 3E */ Prefix | Another,		/* DS:			*/
+    /* 3F */ 0,				/* AAS			*/
+    /* 40 */ 0,				/* INC_RX		*/
+    /* 41 */ 0,				/* INC_RX		*/
+    /* 42 */ 0,				/* INC_RX		*/
+    /* 43 */ 0,				/* INC_RX		*/
+    /* 44 */ 0,				/* INC_RX		*/
+    /* 45 */ 0,				/* INC_RX		*/
+    /* 46 */ 0,				/* INC_RX		*/
+    /* 47 */ 0,				/* INC_RX		*/
+    /* 48 */ 0,				/* DEC_RX		*/
+    /* 49 */ 0,				/* DEC_RX		*/
+    /* 4A */ 0,				/* DEC_RX		*/
+    /* 4B */ 0,				/* DEC_RX		*/
+    /* 4C */ 0,				/* DEC_RX		*/
+    /* 4D */ 0,				/* DEC_RX		*/
+    /* 4E */ 0,				/* DEC_RX		*/
+    /* 4F */ 0,				/* DEC_RX		*/
+    /* 50 */ 0,				/* PUSH_RX		*/
+    /* 51 */ 0,				/* PUSH_RX		*/
+    /* 52 */ 0,				/* PUSH_RX		*/
+    /* 53 */ 0,				/* PUSH_RX		*/
+    /* 54 */ 0,				/* PUSH_RX		*/
+    /* 55 */ 0,				/* PUSH_RX		*/
+    /* 56 */ 0,				/* PUSH_RX		*/
+    /* 57 */ 0,				/* PUSH_RX		*/
+    /* 58 */ 0,				/* POP_RX		*/
+    /* 59 */ 0,				/* POP_RX		*/
+    /* 5A */ 0,				/* POP_RX		*/
+    /* 5B */ 0,				/* POP_RX		*/
+    /* 5C */ 0,				/* POP_RX		*/
+    /* 5D */ 0,				/* POP_RX		*/
+    /* 5E */ 0,				/* POP_RX		*/
+    /* 5F */ 0,				/* POP_RX		*/
+    /* 60 */ 0,				/* PUSHAD16		*/
+    /* 61 */ 0,				/* POPAD16		*/
+    /* 62 */ Another,			/* BOUND_GvMa		*/
+    /* 63 */ Another,			/* ARPL_EwGw		*/
+    /* 64 */ Prefix | Another,		/* FS:			*/
+    /* 65 */ Prefix | Another,		/* GS:			*/
+    /* 66 */ Prefix | Another,		/* OS:			*/
+    /* 67 */ Prefix | Another,		/* AS:			*/
+    /* 68 */ Immediate_Iv,		/* PUSH_Iw		*/
+    /* 69 */ Another | Immediate_Iv,	/* IMUL_GwEwIw		*/
+    /* 6A */ Immediate_Ib_SE,		/* PUSH_Iw		*/
+    /* 6B */ Another | Immediate_Ib_SE, /* IMUL_GwEwIw		*/
+    /* 6C */ Repeatable,		/* INSB_YbDX		*/
+    /* 6D */ Repeatable,		/* INSW_YvDX		*/
+    /* 6E */ Repeatable,		/* OUTSB_DXXb		*/
+    /* 6F */ Repeatable,		/* OUTSW_DXXv		*/
+    /* 70 */ Immediate_BrOff8,		/* JCC_Jw		*/
+    /* 71 */ Immediate_BrOff8,		/* JCC_Jw		*/
+    /* 72 */ Immediate_BrOff8,		/* JCC_Jw		*/
+    /* 73 */ Immediate_BrOff8,		/* JCC_Jw		*/
+    /* 74 */ Immediate_BrOff8,		/* JCC_Jw		*/
+    /* 75 */ Immediate_BrOff8,		/* JCC_Jw		*/
+    /* 76 */ Immediate_BrOff8,		/* JCC_Jw		*/
+    /* 77 */ Immediate_BrOff8,		/* JCC_Jw		*/
+    /* 78 */ Immediate_BrOff8,		/* JCC_Jw		*/
+    /* 79 */ Immediate_BrOff8,		/* JCC_Jw		*/
+    /* 7A */ Immediate_BrOff8,		/* JCC_Jw		*/
+    /* 7B */ Immediate_BrOff8,		/* JCC_Jw		*/
+    /* 7C */ Immediate_BrOff8,		/* JCC_Jw		*/
+    /* 7D */ Immediate_BrOff8,		/* JCC_Jw		*/
+    /* 7E */ Immediate_BrOff8,		/* JCC_Jw		*/
+    /* 7F */ Immediate_BrOff8,		/* JCC_Jw		*/
+    /* 80 */ Another | GroupN | PutGroupIndex (G1EbIb),
+    /* 81 */ Another | GroupN | Immediate_Iv | PutGroupIndex (G1Ew),
+    /* 82 */ Another | GroupN | PutGroupIndex (G1EbIb),
+    /* 83 */ Another | GroupN | Immediate_Ib_SE | PutGroupIndex (G1Ew),
+    /* 84 */ Another,			/* TEST_EbGb		*/
+    /* 85 */ Another,			/* TEST_EwGw		*/
+    /* 86 */ Another,			/* XCHG_EbGb		*/
+    /* 87 */ Another,			/* XCHG_EwGw		*/
+    /* 88 */ Another,			/* MOV_EbGb		*/
+    /* 89 */ Another,			/* MOV_EwGw		*/
+    /* 8A */ Another,			/* MOV_GbEb		*/
+    /* 8B */ Another,			/* MOV_GwEw		*/
+    /* 8C */ Another,			/* MOV_EwSw		*/
+    /* 8D */ Another,			/* LEA_GwM		*/
+    /* 8E */ Another,			/* MOV_SwEw		*/
+    /* 8F */ Another,			/* POP_Ew		*/
+    /* 90 */ 0,				/* NOP			*/
+    /* 91 */ 0,				/* XCHG_RXAX		*/
+    /* 92 */ 0,				/* XCHG_RXAX		*/
+    /* 93 */ 0,				/* XCHG_RXAX		*/
+    /* 94 */ 0,				/* XCHG_RXAX		*/
+    /* 95 */ 0,				/* XCHG_RXAX		*/
+    /* 96 */ 0,				/* XCHG_RXAX		*/
+    /* 97 */ 0,				/* XCHG_RXAX		*/
+    /* 98 */ 0,				/* CBW			*/
+    /* 99 */ 0,				/* CWD			*/
+    /* 9A */ Immediate_IvIw,		/* CALL16_Ap		*/
+    /* 9B */ 0,				/* FWAIT		*/
+    /* 9C */ 0,				/* PUSHF_Fv		*/
+    /* 9D */ 0,				/* POPF_Fv		*/
+    /* 9E */ 0,				/* SAHF			*/
+    /* 9F */ 0,				/* LAHF			*/
+    /* A0 */ Immediate_O,		/* MOV_ALOb		*/
+    /* A1 */ Immediate_O,		/* MOV_AXOw		*/
+    /* A2 */ Immediate_O,		/* MOV_ObAL		*/
+    /* A3 */ Immediate_O,		/* MOV_OwAX		*/
+    /* A4 */ Repeatable,		/* MOVSB_XbYb		*/
+    /* A5 */ Repeatable,		/* MOVSW_XvYv		*/
+    /* A6 */ Repeatable | RepeatableZF,	/* CMPSB_XbYb		*/
+    /* A7 */ Repeatable | RepeatableZF, /* CMPSW_XvYv		*/
+    /* A8 */ Immediate_Ib,		/* TEST_ALIb		*/
+    /* A9 */ Immediate_Iv,		/* TEST_AXIw		*/
+    /* AA */ Repeatable,		/* STOSB_YbAL		*/
+    /* AB */ Repeatable,		/* STOSW_YveAX		*/
+    /* AC */ Repeatable,		/* LODSB_ALXb		*/
+    /* AD */ Repeatable,		/* LODSW_eAXXv		*/
+    /* AE */ Repeatable | RepeatableZF,	/* SCASB_ALXb		*/
+    /* AF */ Repeatable | RepeatableZF,	/* SCASW_eAXXv		*/
+    /* B0 */ Immediate_Ib,		/* MOV_RLIb		*/
+    /* B1 */ Immediate_Ib,		/* MOV_RLIb		*/
+    /* B2 */ Immediate_Ib,		/* MOV_RLIb		*/
+    /* B3 */ Immediate_Ib,		/* MOV_RLIb		*/
+    /* B4 */ Immediate_Ib,		/* MOV_RHIb		*/
+    /* B5 */ Immediate_Ib,		/* MOV_RHIb		*/
+    /* B6 */ Immediate_Ib,		/* MOV_RHIb		*/
+    /* B7 */ Immediate_Ib,		/* MOV_RHIb		*/
+    /* B8 */ Immediate_Iv,		/* MOV_RXIw		*/
+    /* B9 */ Immediate_Iv,		/* MOV_RXIw		*/
+    /* BA */ Immediate_Iv,		/* MOV_RXIw		*/
+    /* BB */ Immediate_Iv,		/* MOV_RXIw		*/
+    /* BC */ Immediate_Iv,		/* MOV_RXIw		*/
+    /* BD */ Immediate_Iv,		/* MOV_RXIw		*/
+    /* BE */ Immediate_Iv,		/* MOV_RXIw		*/
+    /* BF */ Immediate_Iv,		/* MOV_RXIw		*/
+    /* C0 */ Another | GroupN | Immediate_Ib | PutGroupIndex (G2Eb),
+    /* C1 */ Another | GroupN | Immediate_Ib | PutGroupIndex (G2Ew),
+    /* C2 */ Immediate_Iw | UCBranch,	/* RETnear16_Iw		*/
+    /* C3 */ 0 | UCBranch,		/* RETnear16		*/
+    /* C4 */ Another,			/* LES_GvMp		*/
+    /* C5 */ Another,			/* LDS_GvMp		*/
+    /* C6 */ Another | Immediate_Ib,	/* MOV_EbIb		*/
+    /* C7 */ Another | Immediate_Iv,	/* MOV_EwIw		*/
+    /* C8 */ Immediate_IwIb,		/* ENTER_IwIb		*/
+    /* C9 */ 0,				/* LEAVE		*/
+    /* CA */ Immediate_Iw | UCBranch,	/* RETfar16_Iw		*/
+    /* CB */ 0 | UCBranch,		/* RETfar16		*/
+    /* CC */ 0,				/* INT3			*/
+    /* CD */ Immediate_Ib,		/* INT_Ib		*/
+    /* CE */ 0,				/* INTO			*/
+    /* CF */ 0 | UCBranch,		/* IRET16		*/
+    /* D0 */ Another | GroupN | PutGroupIndex (G2Eb),
+    /* D1 */ Another | GroupN | PutGroupIndex (G2Ew),
+    /* D2 */ Another | GroupN | PutGroupIndex (G2Eb),
+    /* D3 */ Another | GroupN | PutGroupIndex (G2Ew),
+    /* D4 */ Immediate_Ib,		/* AAM			*/
+    /* D5 */ Immediate_Ib,		/* AAD			*/
+    /* D6 */ 0,				/* SALC			*/
+    /* D7 */ 0,				/* XLAT			*/
+    /* D8 */ Another,			/* ESC0			*/
+    /* D9 */ Another,			/* ESC1			*/
+    /* DA */ Another,			/* ESC2			*/
+    /* DB */ Another,			/* ESC3			*/
+    /* DC */ Another,			/* ESC4			*/
+    /* DD */ Another,			/* ESC5			*/
+    /* DE */ Another,			/* ESC6			*/
+    /* DF */ Another,			/* ESC7			*/
+    /* E0 */ Immediate_BrOff8,		/* LOOPNE_Jb		*/
+    /* E1 */ Immediate_BrOff8,		/* LOOPE_Jb		*/
+    /* E2 */ Immediate_BrOff8,		/* LOOP_Jb		*/
+    /* E3 */ Immediate_BrOff8,		/* JCXZ_Jb		*/
+    /* E4 */ Immediate_Ib,		/* IN_ALIb		*/
+    /* E5 */ Immediate_Ib,		/* IN_eAXIb		*/
+    /* E6 */ Immediate_Ib,		/* OUT_IbAL		*/
+    /* E7 */ Immediate_Ib,		/* OUT_IbeAX		*/
+    /* E8 */ Immediate_BrOff16,		/* CALL_Aw		*/
+    /* E9 */ Immediate_BrOff16 | UCBranch,	/* JMP_Jw	*/
+    /* EA */ Immediate_IvIw | UCBranch,		/* JMP_Ap	*/
+    /* EB */ Immediate_BrOff8 | UCBranch,	/* JMP_Jb	*/
+    /* EC */ 0,				/* IN_ALDX		*/
+    /* ED */ 0,				/* IN_eAXDX		*/
+    /* EE */ 0,				/* OUT_DXAL		*/
+    /* EF */ 0,				/* OUT_DXeAX		*/
+    /* F0 */ Prefix | Another,		/* LOCK:		*/
+    /* F1 */ 0,				/* INT1			*/
+    /* F2 */ Prefix | Another,		/* REPNE/REPNZ:		*/
+    /* F3 */ Prefix | Another,		/* REP, REPE/REPZ:	*/
+    /* F4 */ 0,				/* HLT			*/
+    /* F5 */ 0,				/* CMC			*/
+    /* F6 */ Another | GroupN | PutGroupIndex (G3Eb),
+    /* F7 */ Another | GroupN | PutGroupIndex (G3Ew),
+    /* F8 */ 0,				/* CLC			*/
+    /* F9 */ 0,				/* STC			*/
+    /* FA */ 0,				/* CLI			*/
+    /* FB */ 0,				/* STI			*/
+    /* FC */ 0,				/* CLD			*/
+    /* FD */ 0,				/* STD			*/
+    /* FE */ Another | GroupN | PutGroupIndex (G4),
+    /* FF */ Another | GroupN | PutGroupIndex (G5w),
+
+    /* 0F 00 */ Another | GroupN | PutGroupIndex (G6),
+    /* 0F 01 */ Another | GroupN | PutGroupIndex (G7),
+    /* 0F 02 */ Another,		/* LAR_GvEw		*/
+    /* 0F 03 */ Another,		/* LSL_GvEw		*/
+    /* 0F 04 */ InvalidOpcode,
+    /* 0F 05 */ 0,			/* LOADALL		*/
+    /* 0F 06 */ 0,			/* CLTS			*/
+    /* 0F 07 */ InvalidOpcode,
+    /* 0F 08 */ 0,			/* INVD			*/
+    /* 0F 09 */ 0,			/* WBINVD		*/
+    /* 0F 0A */ InvalidOpcode,
+    /* 0F 0B */ InvalidOpcode,
+    /* 0F 0C */ InvalidOpcode,
+    /* 0F 0D */ InvalidOpcode,
+    /* 0F 0E */ InvalidOpcode,
+    /* 0F 0F */ InvalidOpcode,
+    /* 0F 10 */ InvalidOpcode,
+    /* 0F 11 */ InvalidOpcode,
+    /* 0F 12 */ InvalidOpcode,
+    /* 0F 13 */ InvalidOpcode,
+    /* 0F 14 */ InvalidOpcode,
+    /* 0F 15 */ InvalidOpcode,
+    /* 0F 16 */ InvalidOpcode,
+    /* 0F 17 */ InvalidOpcode,
+    /* 0F 18 */ InvalidOpcode,
+    /* 0F 19 */ InvalidOpcode,
+    /* 0F 1A */ InvalidOpcode,
+    /* 0F 1B */ InvalidOpcode,
+    /* 0F 1C */ InvalidOpcode,
+    /* 0F 1D */ InvalidOpcode,
+    /* 0F 1E */ InvalidOpcode,
+    /* 0F 1F */ InvalidOpcode,
+    /* 0F 20 */ Another,		/* MOV_RdCd		*/
+    /* 0F 21 */ Another,		/* MOV_RdDd		*/
+    /* 0F 22 */ Another,		/* MOV_CdRd		*/
+    /* 0F 23 */ Another,		/* MOV_DdRd		*/
+    /* 0F 24 */ Another,		/* MOV_RdTd		*/
+    /* 0F 25 */ InvalidOpcode,
+    /* 0F 26 */ Another,		/* MOV_TdRd		*/
+    /* 0F 27 */ InvalidOpcode,
+    /* 0F 28 */ InvalidOpcode,
+    /* 0F 29 */ InvalidOpcode,
+    /* 0F 2A */ InvalidOpcode,
+    /* 0F 2B */ InvalidOpcode,
+    /* 0F 2C */ InvalidOpcode,
+    /* 0F 2D */ InvalidOpcode,
+    /* 0F 2E */ InvalidOpcode,
+    /* 0F 2F */ InvalidOpcode,
+    /* 0F 30 */ 0,			/* WRMSR		*/
+    /* 0F 31 */ 0,			/* RDTSC		*/
+    /* 0F 32 */ 0,			/* RDMSR		*/
+    /* 0F 33 */ InvalidOpcode,
+    /* 0F 34 */ InvalidOpcode,
+    /* 0F 35 */ InvalidOpcode,
+    /* 0F 36 */ InvalidOpcode,
+    /* 0F 37 */ InvalidOpcode,
+    /* 0F 38 */ InvalidOpcode,
+    /* 0F 39 */ InvalidOpcode,
+    /* 0F 3A */ InvalidOpcode,
+    /* 0F 3B */ InvalidOpcode,
+    /* 0F 3C */ InvalidOpcode,
+    /* 0F 3D */ InvalidOpcode,
+    /* 0F 3E */ InvalidOpcode,
+    /* 0F 3F */ InvalidOpcode,
+    /* 0F 40 */ Another,		/* CMOV_GwEw		*/
+    /* 0F 41 */ Another,		/* CMOV_GwEw		*/
+    /* 0F 42 */ Another,		/* CMOV_GwEw		*/
+    /* 0F 43 */ Another,		/* CMOV_GwEw		*/
+    /* 0F 44 */ Another,		/* CMOV_GwEw		*/
+    /* 0F 45 */ Another,		/* CMOV_GwEw		*/
+    /* 0F 46 */ Another,		/* CMOV_GwEw		*/
+    /* 0F 47 */ Another,		/* CMOV_GwEw		*/
+    /* 0F 48 */ Another,		/* CMOV_GwEw		*/
+    /* 0F 49 */ Another,		/* CMOV_GwEw		*/
+    /* 0F 4A */ Another,		/* CMOV_GwEw		*/
+    /* 0F 4B */ Another,		/* CMOV_GwEw		*/
+    /* 0F 4C */ Another,		/* CMOV_GwEw		*/
+    /* 0F 4D */ Another,		/* CMOV_GwEw		*/
+    /* 0F 4E */ Another,		/* CMOV_GwEw		*/
+    /* 0F 4F */ Another,		/* CMOV_GwEw		*/
+    /* 0F 50 */ InvalidOpcode,
+    /* 0F 51 */ InvalidOpcode,
+    /* 0F 52 */ InvalidOpcode,
+    /* 0F 53 */ InvalidOpcode,
+    /* 0F 54 */ InvalidOpcode,
+    /* 0F 55 */ InvalidOpcode,
+    /* 0F 56 */ InvalidOpcode,
+    /* 0F 57 */ InvalidOpcode,
+    /* 0F 58 */ InvalidOpcode,
+    /* 0F 59 */ InvalidOpcode,
+    /* 0F 5A */ InvalidOpcode,
+    /* 0F 5B */ InvalidOpcode,
+    /* 0F 5C */ InvalidOpcode,
+    /* 0F 5D */ InvalidOpcode,
+    /* 0F 5E */ InvalidOpcode,
+    /* 0F 5F */ InvalidOpcode,
+    /* 0F 60 */ InvalidOpcode,
+    /* 0F 61 */ InvalidOpcode,
+    /* 0F 62 */ InvalidOpcode,
+    /* 0F 63 */ InvalidOpcode,
+    /* 0F 64 */ InvalidOpcode,
+    /* 0F 65 */ InvalidOpcode,
+    /* 0F 66 */ InvalidOpcode,
+    /* 0F 67 */ InvalidOpcode,
+    /* 0F 68 */ InvalidOpcode,
+    /* 0F 69 */ InvalidOpcode,
+    /* 0F 6A */ InvalidOpcode,
+    /* 0F 6B */ InvalidOpcode,
+    /* 0F 6C */ InvalidOpcode,
+    /* 0F 6D */ InvalidOpcode,
+    /* 0F 6E */ InvalidOpcode,
+    /* 0F 6F */ InvalidOpcode,
+    /* 0F 70 */ InvalidOpcode,
+    /* 0F 71 */ InvalidOpcode,
+    /* 0F 72 */ InvalidOpcode,
+    /* 0F 73 */ InvalidOpcode,
+    /* 0F 74 */ InvalidOpcode,
+    /* 0F 75 */ InvalidOpcode,
+    /* 0F 76 */ InvalidOpcode,
+    /* 0F 77 */ InvalidOpcode,
+    /* 0F 78 */ InvalidOpcode,
+    /* 0F 79 */ InvalidOpcode,
+    /* 0F 7A */ InvalidOpcode,
+    /* 0F 7B */ InvalidOpcode,
+    /* 0F 7C */ InvalidOpcode,
+    /* 0F 7D */ InvalidOpcode,
+    /* 0F 7E */ InvalidOpcode,
+    /* 0F 7F */ InvalidOpcode,
+    /* 0F 80 */ Immediate_BrOff16,	/* JCC_Jw		*/
+    /* 0F 81 */ Immediate_BrOff16,	/* JCC_Jw		*/
+    /* 0F 82 */ Immediate_BrOff16,	/* JCC_Jw		*/
+    /* 0F 83 */ Immediate_BrOff16,	/* JCC_Jw		*/
+    /* 0F 84 */ Immediate_BrOff16,	/* JCC_Jw		*/
+    /* 0F 85 */ Immediate_BrOff16,	/* JCC_Jw		*/
+    /* 0F 86 */ Immediate_BrOff16,	/* JCC_Jw		*/
+    /* 0F 87 */ Immediate_BrOff16,	/* JCC_Jw		*/
+    /* 0F 88 */ Immediate_BrOff16,	/* JCC_Jw		*/
+    /* 0F 89 */ Immediate_BrOff16,	/* JCC_Jw		*/
+    /* 0F 8A */ Immediate_BrOff16,	/* JCC_Jw		*/
+    /* 0F 8B */ Immediate_BrOff16,	/* JCC_Jw		*/
+    /* 0F 8C */ Immediate_BrOff16,	/* JCC_Jw		*/
+    /* 0F 8D */ Immediate_BrOff16,	/* JCC_Jw		*/
+    /* 0F 8E */ Immediate_BrOff16,	/* JCC_Jw		*/
+    /* 0F 8F */ Immediate_BrOff16,	/* JCC_Jw		*/
+    /* 0F 90 */ Another,		/* SETO_Eb		*/
+    /* 0F 91 */ Another,		/* SETNO_Eb		*/
+    /* 0F 92 */ Another,		/* SETB_Eb		*/
+    /* 0F 93 */ Another,		/* SETNB_Eb		*/
+    /* 0F 94 */ Another,		/* SETZ_Eb		*/
+    /* 0F 95 */ Another,		/* SETNZ_Eb		*/
+    /* 0F 96 */ Another,		/* SETBE_Eb		*/
+    /* 0F 97 */ Another,		/* SETNBE_Eb		*/
+    /* 0F 98 */ Another,		/* SETS_Eb		*/
+    /* 0F 99 */ Another,		/* SETNS_Eb		*/
+    /* 0F 9A */ Another,		/* SETP_Eb		*/
+    /* 0F 9B */ Another,		/* SETNP_Eb		*/
+    /* 0F 9C */ Another,		/* SETL_Eb		*/
+    /* 0F 9D */ Another,		/* SETNL_Eb		*/
+    /* 0F 9E */ Another,		/* SETLE_Eb		*/
+    /* 0F 9F */ Another,		/* SETNLE_Eb		*/
+    /* 0F A0 */ 0,			/* PUSH_FS		*/
+    /* 0F A1 */ 0,			/* POP_FS		*/
+    /* 0F A2 */ 0,			/* CPUID		*/
+    /* 0F A3 */ Another,		/* BT_EvGv		*/
+    /* 0F A4 */ Another | Immediate_Ib,	/* SHLD_EwGw		*/
+    /* 0F A5 */ Another,		/* SHLD_EwGw		*/
+    /* 0F A6 */ 0,			/* CMPXCHG_XBTS		*/
+    /* 0F A7 */ 0,			/* CMPXCHG_IBTS		*/
+    /* 0F A8 */ 0,			/* PUSH_GS		*/
+    /* 0F A9 */ 0,			/* POP_GS		*/
+    /* 0F AA */ 0,			/* RSM			*/
+    /* 0F AB */ Another,		/* BTS_EvGv		*/
+    /* 0F AC */ Another | Immediate_Ib,	/* SHRD_EwGw		*/
+    /* 0F AD */ Another,		/* SHRD_EwGw		*/
+    /* 0F AE */ InvalidOpcode,
+    /* 0F AF */ Another,		/* IMUL_GwEw		*/
+    /* 0F B0 */ Another,		/* CMPXCHG_EbGb		*/
+    /* 0F B1 */ Another,		/* CMPXCHG_EwGw		*/
+    /* 0F B2 */ Another,		/* LSS_GvMp		*/
+    /* 0F B3 */ Another,		/* BTR_EvGv		*/
+    /* 0F B4 */ Another,		/* LFS_GvMp		*/
+    /* 0F B5 */ Another,		/* LGS_GvMp		*/
+    /* 0F B6 */ Another,		/* MOVZX_GwEb		*/
+    /* 0F B7 */ Another,		/* MOVZX_GwEw		*/
+    /* 0F B8 */ InvalidOpcode,
+    /* 0F B9 */ InvalidOpcode,
+    /* 0F BA */ Another | GroupN | PutGroupIndex (G8EvIb),
+    /* 0F BB */ Another,		/* BTC_EvGv		*/
+    /* 0F BC */ Another,		/* BSF_GvEv		*/
+    /* 0F BD */ Another,		/* BSR_GvEv		*/
+    /* 0F BE */ Another,		/* MOVSX_GwEb		*/
+    /* 0F BF */ Another,		/* MOVSX_GwEw		*/
+    /* 0F C0 */ Another,		/* XADD_EbGb		*/
+    /* 0F C1 */ Another,		/* XADD_EwGw		*/
+    /* 0F C2 */ InvalidOpcode,
+    /* 0F C3 */ InvalidOpcode,
+    /* 0F C4 */ InvalidOpcode,
+    /* 0F C5 */ InvalidOpcode,
+    /* 0F C6 */ InvalidOpcode,
+    /* 0F C7 */ Another | GroupN | PutGroupIndex (G9),
+    /* 0F C8 */ 0,			/* BSWAP_EAX		*/
+    /* 0F C9 */ 0,			/* BSWAP_ECX		*/
+    /* 0F CA */ 0,			/* BSWAP_EDX		*/
+    /* 0F CB */ 0,			/* BSWAP_EBX		*/
+    /* 0F CC */ 0,			/* BSWAP_ESP		*/
+    /* 0F CD */ 0,			/* BSWAP_EBP		*/
+    /* 0F CE */ 0,			/* BSWAP_ESI		*/
+    /* 0F CF */ 0,			/* BSWAP_EDI		*/
+    /* 0F D0 */ InvalidOpcode,
+    /* 0F D1 */ InvalidOpcode,
+    /* 0F D2 */ InvalidOpcode,
+    /* 0F D3 */ InvalidOpcode,
+    /* 0F D4 */ InvalidOpcode,
+    /* 0F D5 */ InvalidOpcode,
+    /* 0F D6 */ InvalidOpcode,
+    /* 0F D7 */ InvalidOpcode,
+    /* 0F D8 */ InvalidOpcode,
+    /* 0F D9 */ InvalidOpcode,
+    /* 0F DA */ InvalidOpcode,
+    /* 0F DB */ InvalidOpcode,
+    /* 0F DC */ InvalidOpcode,
+    /* 0F DD */ InvalidOpcode,
+    /* 0F DE */ InvalidOpcode,
+    /* 0F DF */ InvalidOpcode,
+    /* 0F E0 */ InvalidOpcode,
+    /* 0F E1 */ InvalidOpcode,
+    /* 0F E2 */ InvalidOpcode,
+    /* 0F E3 */ InvalidOpcode,
+    /* 0F E4 */ InvalidOpcode,
+    /* 0F E5 */ InvalidOpcode,
+    /* 0F E6 */ InvalidOpcode,
+    /* 0F E7 */ InvalidOpcode,
+    /* 0F E8 */ InvalidOpcode,
+    /* 0F E9 */ InvalidOpcode,
+    /* 0F EA */ InvalidOpcode,
+    /* 0F EB */ InvalidOpcode,
+    /* 0F EC */ InvalidOpcode,
+    /* 0F ED */ InvalidOpcode,
+    /* 0F EE */ InvalidOpcode,
+    /* 0F EF */ InvalidOpcode,
+    /* 0F F0 */ InvalidOpcode,
+    /* 0F F1 */ InvalidOpcode,
+    /* 0F F2 */ InvalidOpcode,
+    /* 0F F3 */ InvalidOpcode,
+    /* 0F F4 */ InvalidOpcode,
+    /* 0F F5 */ InvalidOpcode,
+    /* 0F F6 */ InvalidOpcode,
+    /* 0F F7 */ InvalidOpcode,
+    /* 0F F8 */ InvalidOpcode,
+    /* 0F F9 */ InvalidOpcode,
+    /* 0F FA */ InvalidOpcode,
+    /* 0F FB */ InvalidOpcode,
+    /* 0F FC */ InvalidOpcode,
+    /* 0F FD */ InvalidOpcode,
+    /* 0F FE */ InvalidOpcode,
+    /* 0F FF */ InvalidOpcode,
+
+/* 512 entries for 32bit mod */
+    /* 00 */ Another,			/* ADD_EbGb		*/
+    /* 01 */ Another,			/* ADD_EdGd		*/
+    /* 02 */ Another,			/* ADD_GbEb		*/
+    /* 03 */ Another,			/* ADD_GdEd		*/
+    /* 04 */ Immediate_Ib,		/* ADD_ALIb		*/
+    /* 05 */ Immediate_Iv,		/* ADD_EAXId		*/
+    /* 06 */ 0,				/* PUSH_ES		*/
+    /* 07 */ 0,				/* POP_ES		*/
+    /* 08 */ Another,			/* OR_EbGb		*/
+    /* 09 */ Another,			/* OR_EdGd		*/
+    /* 0A */ Another,			/* OR_GbEb		*/
+    /* 0B */ Another,			/* OR_GdEd		*/
+    /* 0C */ Immediate_Ib,		/* OR_ALIb		*/
+    /* 0D */ Immediate_Iv,		/* OR_EAXId		*/
+    /* 0E */ 0,				/* PUSH_CS		*/
+    /* 0F */ Another,			/* 2-byte escape	*/
+    /* 10 */ Another,			/* ADC_EbGb		*/
+    /* 11 */ Another,			/* ADC_EdGd		*/
+    /* 12 */ Another,			/* ADC_GbEb		*/
+    /* 13 */ Another,			/* ADC_GdEd		*/
+    /* 14 */ Immediate_Ib,		/* ADC_ALIb		*/
+    /* 15 */ Immediate_Iv,		/* ADC_EAXId		*/
+    /* 16 */ 0,				/* PUSH_SS		*/
+    /* 17 */ 0,				/* POP_SS		*/
+    /* 18 */ Another,			/* SBB_EbGb		*/
+    /* 19 */ Another,			/* SBB_EdGd		*/
+    /* 1A */ Another,			/* SBB_GbEb		*/
+    /* 1B */ Another,			/* SBB_GdEd		*/
+    /* 1C */ Immediate_Ib,		/* SBB_ALIb		*/
+    /* 1D */ Immediate_Iv,		/* SBB_EAXId		*/
+    /* 1E */ 0,				/* PUSH_DS		*/
+    /* 1F */ 0,				/* POP_DS		*/
+    /* 20 */ Another,			/* AND_EbGb		*/
+    /* 21 */ Another,			/* AND_EdGd		*/
+    /* 22 */ Another,			/* AND_GbEb		*/
+    /* 23 */ Another,			/* AND_GdEd		*/
+    /* 24 */ Immediate_Ib,		/* AND_ALIb		*/
+    /* 25 */ Immediate_Iv,		/* AND_EAXId		*/
+    /* 26 */ Prefix | Another,		/* ES:			*/
+    /* 27 */ 0,				/* DAA			*/
+    /* 28 */ Another,			/* SUB_EbGb		*/
+    /* 29 */ Another,			/* SUB_EdGd		*/
+    /* 2A */ Another,			/* SUB_GbEb		*/
+    /* 2B */ Another,			/* SUB_GdEd		*/
+    /* 2C */ Immediate_Ib,		/* SUB_ALIb		*/
+    /* 2D */ Immediate_Iv,		/* SUB_EAXId		*/
+    /* 2E */ Prefix | Another,		/* CS:			*/
+    /* 2F */ 0,				/* DAS			*/
+    /* 30 */ Another,			/* XOR_EbGb		*/
+    /* 31 */ Another,			/* XOR_EdGd		*/
+    /* 32 */ Another,			/* XOR_GbEb		*/
+    /* 33 */ Another,			/* XOR_GdEd		*/
+    /* 34 */ Immediate_Ib,		/* XOR_ALIb		*/
+    /* 35 */ Immediate_Iv,		/* XOR_EAXId		*/
+    /* 36 */ Prefix | Another,		/* SS:			*/
+    /* 37 */ 0,				/* AAA			*/
+    /* 38 */ Another,			/* CMP_EbGb		*/
+    /* 39 */ Another,			/* CMP_EdGd		*/
+    /* 3A */ Another,			/* CMP_GbEb		*/
+    /* 3B */ Another,			/* CMP_GdEd		*/
+    /* 3C */ Immediate_Ib,		/* CMP_ALIb		*/
+    /* 3D */ Immediate_Iv,		/* CMP_EAXId		*/
+    /* 3E */ Prefix | Another,		/* DS:			*/
+    /* 3F */ 0,				/* AAS			*/
+    /* 40 */ 0,				/* INC_ERX		*/
+    /* 41 */ 0,				/* INC_ERX		*/
+    /* 42 */ 0,				/* INC_ERX		*/
+    /* 43 */ 0,				/* INC_ERX		*/
+    /* 44 */ 0,				/* INC_ERX		*/
+    /* 45 */ 0,				/* INC_ERX		*/
+    /* 46 */ 0,				/* INC_ERX		*/
+    /* 47 */ 0,				/* INC_ERX		*/
+    /* 48 */ 0,				/* DEC_ERX		*/
+    /* 49 */ 0,				/* DEC_ERX		*/
+    /* 4A */ 0,				/* DEC_ERX		*/
+    /* 4B */ 0,				/* DEC_ERX		*/
+    /* 4C */ 0,				/* DEC_ERX		*/
+    /* 4D */ 0,				/* DEC_ERX		*/
+    /* 4E */ 0,				/* DEC_ERX		*/
+    /* 4F */ 0,				/* DEC_ERX		*/
+    /* 50 */ 0,				/* PUSH_ERX		*/
+    /* 51 */ 0,				/* PUSH_ERX		*/
+    /* 52 */ 0,				/* PUSH_ERX		*/
+    /* 53 */ 0,				/* PUSH_ERX		*/
+    /* 54 */ 0,				/* PUSH_ERX		*/
+    /* 55 */ 0,				/* PUSH_ERX		*/
+    /* 56 */ 0,				/* PUSH_ERX		*/
+    /* 57 */ 0,				/* PUSH_ERX		*/
+    /* 58 */ 0,				/* POP_ERX		*/
+    /* 59 */ 0,				/* POP_ERX		*/
+    /* 5A */ 0,				/* POP_ERX		*/
+    /* 5B */ 0,				/* POP_ERX		*/
+    /* 5C */ 0,				/* POP_ERX		*/
+    /* 5D */ 0,				/* POP_ERX		*/
+    /* 5E */ 0,				/* POP_ERX		*/
+    /* 5F */ 0,				/* POP_ERX		*/
+    /* 60 */ 0,				/* PUSHAD32		*/
+    /* 61 */ 0,				/* POPAD32		*/
+    /* 62 */ Another,			/* BOUND_GvMa		*/
+    /* 63 */ Another,			/* ARPL_EwGw		*/
+    /* 64 */ Prefix | Another,		/* FS:			*/
+    /* 65 */ Prefix | Another,		/* GS:			*/
+    /* 66 */ Prefix | Another,		/* OS:			*/
+    /* 67 */ Prefix | Another,		/* AS:			*/
+    /* 68 */ Immediate_Iv,		/* PUSH_Id		*/
+    /* 69 */ Another | Immediate_Iv,	/* IMUL_GdEdId		*/
+    /* 6A */ Immediate_Ib_SE,		/* PUSH_Id		*/
+    /* 6B */ Another | Immediate_Ib_SE,	/* IMUL_GdEdId		*/
+    /* 6C */ Repeatable,		/* INSB_YbDX		*/
+    /* 6D */ Repeatable,		/* INSW_YvDX		*/
+    /* 6E */ Repeatable,		/* OUTSB_DXXb		*/
+    /* 6F */ Repeatable,		/* OUTSW_DXXv		*/
+    /* 70 */ Immediate_BrOff8,		/* JCC_Jd		*/
+    /* 71 */ Immediate_BrOff8,		/* JCC_Jd		*/
+    /* 72 */ Immediate_BrOff8,		/* JCC_Jd		*/
+    /* 73 */ Immediate_BrOff8,		/* JCC_Jd		*/
+    /* 74 */ Immediate_BrOff8,		/* JCC_Jd		*/
+    /* 75 */ Immediate_BrOff8,		/* JCC_Jd		*/
+    /* 76 */ Immediate_BrOff8,		/* JCC_Jd		*/
+    /* 77 */ Immediate_BrOff8,		/* JCC_Jd		*/
+    /* 78 */ Immediate_BrOff8,		/* JCC_Jd		*/
+    /* 79 */ Immediate_BrOff8,		/* JCC_Jd		*/
+    /* 7A */ Immediate_BrOff8,		/* JCC_Jd		*/
+    /* 7B */ Immediate_BrOff8,		/* JCC_Jd		*/
+    /* 7C */ Immediate_BrOff8,		/* JCC_Jd		*/
+    /* 7D */ Immediate_BrOff8,		/* JCC_Jd		*/
+    /* 7E */ Immediate_BrOff8,		/* JCC_Jd		*/
+    /* 7F */ Immediate_BrOff8,		/* JCC_Jd		*/
+    /* 80 */ Another | GroupN | PutGroupIndex (G1EbIb),
+    /* 81 */ Another | GroupN | Immediate_Iv | PutGroupIndex (G1Ed),
+    /* 82 */ Another | GroupN | PutGroupIndex (G1EbIb),
+    /* 83 */ Another | GroupN | Immediate_Ib_SE | PutGroupIndex (G1Ed),
+    /* 84 */ Another,			/* TEST_EbGb		*/
+    /* 85 */ Another,			/* TEST_EdGd		*/
+    /* 86 */ Another,			/* XCHG_EbGb		*/
+    /* 87 */ Another,			/* XCHG_EdGd		*/
+    /* 88 */ Another,			/* MOV_EbGb		*/
+    /* 89 */ Another,			/* MOV_EdGd		*/
+    /* 8A */ Another,			/* MOV_GbEb		*/
+    /* 8B */ Another,			/* MOV_GdEd		*/
+    /* 8C */ Another,			/* MOV_EwSw		*/
+    /* 8D */ Another,			/* LEA_GdM		*/
+    /* 8E */ Another,			/* MOV_SwEw		*/
+    /* 8F */ Another,			/* POP_Ed		*/
+    /* 90 */ 0,				/* NOP			*/
+    /* 91 */ 0,				/* XCHG_ERXEAX		*/
+    /* 92 */ 0,				/* XCHG_ERXEAX		*/
+    /* 93 */ 0,				/* XCHG_ERXEAX		*/
+    /* 94 */ 0,				/* XCHG_ERXEAX		*/
+    /* 95 */ 0,				/* XCHG_ERXEAX		*/
+    /* 96 */ 0,				/* XCHG_ERXEAX		*/
+    /* 97 */ 0,				/* XCHG_ERXEAX		*/
+    /* 98 */ 0,				/* CWDE			*/
+    /* 99 */ 0,				/* CDQ			*/
+    /* 9A */ Immediate_IvIw,		/* CALL32_Ap		*/
+    /* 9B */ 0,				/* FWAIT		*/
+    /* 9C */ 0,				/* PUSHF_Fv		*/
+    /* 9D */ 0,				/* POPF_Fv		*/
+    /* 9E */ 0,				/* SAHF			*/
+    /* 9F */ 0,				/* LAHF			*/
+    /* A0 */ Immediate_O,		/* MOV_ALOb		*/
+    /* A1 */ Immediate_O,		/* MOV_EAXOd		*/
+    /* A2 */ Immediate_O,		/* MOV_ObAL		*/
+    /* A3 */ Immediate_O,		/* MOV_OdEAX		*/
+    /* A4 */ Repeatable,		/* MOVSB_XbYb		*/
+    /* A5 */ Repeatable,		/* MOVSW_XvYv		*/
+    /* A6 */ Repeatable | RepeatableZF,	/* CMPSB_XbYb		*/
+    /* A7 */ Repeatable | RepeatableZF,	/* CMPSW_XvYv		*/
+    /* A8 */ Immediate_Ib,		/* TEST_ALIb		*/
+    /* A9 */ Immediate_Iv,		/* TEST_EAXId		*/
+    /* AA */ Repeatable,		/* STOSB_YbAL		*/
+    /* AB */ Repeatable,		/* STOSW_YveAX		*/
+    /* AC */ Repeatable,		/* LODSB_ALXb		*/
+    /* AD */ Repeatable,		/* LODSW_eAXXv		*/
+    /* AE */ Repeatable | RepeatableZF,	/* SCASB_ALXb		*/
+    /* AF */ Repeatable | RepeatableZF,	/* SCASW_eAXXv		*/
+    /* B0 */ Immediate_Ib,		/* MOV_RLIb		*/
+    /* B1 */ Immediate_Ib,		/* MOV_RLIb		*/
+    /* B2 */ Immediate_Ib,		/* MOV_RLIb		*/
+    /* B3 */ Immediate_Ib,		/* MOV_RLIb		*/
+    /* B4 */ Immediate_Ib,		/* MOV_RHIb		*/
+    /* B5 */ Immediate_Ib,		/* MOV_RHIb		*/
+    /* B6 */ Immediate_Ib,		/* MOV_RHIb		*/
+    /* B7 */ Immediate_Ib,		/* MOV_RHIb		*/
+    /* B8 */ Immediate_Iv,		/* MOV_ERXId		*/
+    /* B9 */ Immediate_Iv,		/* MOV_ERXId		*/
+    /* BA */ Immediate_Iv,		/* MOV_ERXId		*/
+    /* BB */ Immediate_Iv,		/* MOV_ERXId		*/
+    /* BC */ Immediate_Iv,		/* MOV_ERXId		*/
+    /* BD */ Immediate_Iv,		/* MOV_ERXId		*/
+    /* BE */ Immediate_Iv,		/* MOV_ERXId		*/
+    /* BF */ Immediate_Iv,		/* MOV_ERXId		*/
+    /* C0 */ Another | GroupN | Immediate_Ib | PutGroupIndex (G2Eb),
+    /* C1 */ Another | GroupN | Immediate_Ib | PutGroupIndex (G2Ed),
+    /* C2 */ Immediate_Iw | UCBranch,	/* RETnear32_Iw		*/
+    /* C3 */ 0 | UCBranch,		/* RETnear32		*/
+    /* C4 */ Another,			/* LES_GvMp		*/
+    /* C5 */ Another,			/* LDS_GvMp		*/
+    /* C6 */ Another | Immediate_Ib,	/* MOV_EbIb		*/
+    /* C7 */ Another | Immediate_Iv,	/* MOV_EdId		*/
+    /* C8 */ Immediate_IwIb,		/* ENTER_IwIb		*/
+    /* C9 */ 0,				/* LEAVE		*/
+    /* CA */ Immediate_Iw | UCBranch,	/* RETfar32_Iw		*/
+    /* CB */ 0 | UCBranch,		/* RETfar32		*/
+    /* CC */ 0,				/* INT3			*/
+    /* CD */ Immediate_Ib,		/* INT_Ib		*/
+    /* CE */ 0,				/* INTO			*/
+    /* CF */ 0 | UCBranch,		/* IRET32		*/
+    /* D0 */ Another | GroupN | PutGroupIndex (G2Eb),
+    /* D1 */ Another | GroupN | PutGroupIndex (G2Ed),
+    /* D2 */ Another | GroupN | PutGroupIndex (G2Eb),
+    /* D3 */ Another | GroupN | PutGroupIndex (G2Ed),
+    /* D4 */ Immediate_Ib,		/* AAM			*/
+    /* D5 */ Immediate_Ib,		/* AAD			*/
+    /* D6 */ 0,				/* SALC			*/
+    /* D7 */ 0,				/* XLAT			*/
+    /* D8 */ Another,			/* ESC0			*/
+    /* D9 */ Another,			/* ESC1			*/
+    /* DA */ Another,			/* ESC2			*/
+    /* DB */ Another,			/* ESC3			*/
+    /* DC */ Another,			/* ESC4			*/
+    /* DD */ Another,			/* ESC5			*/
+    /* DE */ Another,			/* ESC6			*/
+    /* DF */ Another,			/* ESC7			*/
+    /* E0 */ Immediate_BrOff8,		/* LOOPNE_Jb		*/
+    /* E1 */ Immediate_BrOff8,		/* LOOPE_Jb		*/
+    /* E2 */ Immediate_BrOff8,		/* LOOP_Jb		*/
+    /* E3 */ Immediate_BrOff8,		/* JCXZ_Jb		*/
+    /* E4 */ Immediate_Ib,		/* IN_ALIb		*/
+    /* E5 */ Immediate_Ib,		/* IN_eAXIb		*/
+    /* E6 */ Immediate_Ib,		/* OUT_IbAL		*/
+    /* E7 */ Immediate_Ib,		/* OUT_IbeAX		*/
+    /* E8 */ Immediate_BrOff32,		/* CALL_Ad		*/
+    /* E9 */ Immediate_BrOff32 | UCBranch,	/* JMP_Jd	*/
+    /* EA */ Immediate_IvIw | UCBranch,		/* JMP_Ap	*/
+    /* EB */ Immediate_BrOff8 | UCBranch,	/* JMP_Jb	*/
+    /* EC */ 0,				/* IN_ALDX		*/
+    /* ED */ 0,				/* IN_eAXDX		*/
+    /* EE */ 0,				/* OUT_DXAL		*/
+    /* EF */ 0,				/* OUT_DXeAX		*/
+    /* F0 */ Prefix | Another,		/* LOCK:		*/
+    /* F1 */ 0,				/* INT1			*/
+    /* F2 */ Prefix | Another,		/* REPNE/REPNZ:		*/
+    /* F3 */ Prefix | Another,		/* REP,REPE/REPZ:	*/
+    /* F4 */ 0,				/* HLT			*/
+    /* F5 */ 0,				/* CMC			*/
+    /* F6 */ Another | GroupN | PutGroupIndex (G3Eb),
+    /* F7 */ Another | GroupN | PutGroupIndex (G3Ed),
+    /* F8 */ 0,				/* CLC			*/
+    /* F9 */ 0,				/* STC			*/
+    /* FA */ 0,				/* CLI			*/
+    /* FB */ 0,				/* STI			*/
+    /* FC */ 0,				/* CLD			*/
+    /* FD */ 0,				/* STD			*/
+    /* FE */ Another | GroupN | PutGroupIndex (G4),
+    /* FF */ Another | GroupN | PutGroupIndex (G5d),
+
+    /* 0F 00 */ Another | GroupN | PutGroupIndex (G6),
+    /* 0F 01 */ Another | GroupN | PutGroupIndex (G7),
+    /* 0F 02 */ Another,		/* LAR_GvEw		*/
+    /* 0F 03 */ Another,		/* LSL_GvEw		*/
+    /* 0F 04 */ InvalidOpcode,		
+    /* 0F 05 */ 0,			/* LOADALL		*/
+    /* 0F 06 */ 0,			/* CLTS			*/
+    /* 0F 07 */ InvalidOpcode,
+    /* 0F 08 */ 0,			/* INVD			*/
+    /* 0F 09 */ 0,			/* WBINVD		*/
+    /* 0F 0A */ InvalidOpcode,
+    /* 0F 0B */ InvalidOpcode,
+    /* 0F 0C */ InvalidOpcode,
+    /* 0F 0D */ InvalidOpcode,
+    /* 0F 0E */ InvalidOpcode,
+    /* 0F 0F */ InvalidOpcode,
+    /* 0F 10 */ InvalidOpcode,
+    /* 0F 11 */ InvalidOpcode,
+    /* 0F 12 */ InvalidOpcode,
+    /* 0F 13 */ InvalidOpcode,
+    /* 0F 14 */ InvalidOpcode,
+    /* 0F 15 */ InvalidOpcode,
+    /* 0F 16 */ InvalidOpcode,
+    /* 0F 17 */ InvalidOpcode,
+    /* 0F 18 */ InvalidOpcode,
+    /* 0F 19 */ InvalidOpcode,
+    /* 0F 1A */ InvalidOpcode,
+    /* 0F 1B */ InvalidOpcode,
+    /* 0F 1C */ InvalidOpcode,
+    /* 0F 1D */ InvalidOpcode,
+    /* 0F 1E */ InvalidOpcode,
+    /* 0F 1F */ InvalidOpcode,
+    /* 0F 20 */ Another,		/* MOV_RdCd		*/
+    /* 0F 21 */ Another,		/* MOV_RdDd		*/
+    /* 0F 22 */ Another,		/* MOV_CdRd		*/
+    /* 0F 23 */ Another,		/* MOV_DdRd		*/
+    /* 0F 24 */ Another,		/* MOV_RdTd		*/
+    /* 0F 25 */ InvalidOpcode,
+    /* 0F 26 */ Another,		/* MOV_TdRd		*/
+    /* 0F 27 */ InvalidOpcode,
+    /* 0F 28 */ InvalidOpcode,
+    /* 0F 29 */ InvalidOpcode,
+    /* 0F 2A */ InvalidOpcode,
+    /* 0F 2B */ InvalidOpcode,
+    /* 0F 2C */ InvalidOpcode,
+    /* 0F 2D */ InvalidOpcode,
+    /* 0F 2E */ InvalidOpcode,
+    /* 0F 2F */ InvalidOpcode,
+    /* 0F 30 */ 0,			/* WRMSR		*/
+    /* 0F 31 */ 0,			/* RDTSC		*/
+    /* 0F 32 */ 0,			/* RDMSR		*/
+    /* 0F 33 */ InvalidOpcode,
+    /* 0F 34 */ InvalidOpcode,
+    /* 0F 35 */ InvalidOpcode,
+    /* 0F 36 */ InvalidOpcode,
+    /* 0F 37 */ InvalidOpcode,
+    /* 0F 38 */ InvalidOpcode,
+    /* 0F 39 */ InvalidOpcode,
+    /* 0F 3A */ InvalidOpcode,
+    /* 0F 3B */ InvalidOpcode,
+    /* 0F 3C */ InvalidOpcode,
+    /* 0F 3D */ InvalidOpcode,
+    /* 0F 3E */ InvalidOpcode,
+    /* 0F 3F */ InvalidOpcode,
+    /* 0F 40 */ Another,		/* CMOV_GdEd		*/
+    /* 0F 41 */ Another,		/* CMOV_GdEd		*/
+    /* 0F 42 */ Another,		/* CMOV_GdEd		*/
+    /* 0F 43 */ Another,		/* CMOV_GdEd		*/
+    /* 0F 44 */ Another,		/* CMOV_GdEd		*/
+    /* 0F 45 */ Another,		/* CMOV_GdEd		*/
+    /* 0F 46 */ Another,		/* CMOV_GdEd		*/
+    /* 0F 47 */ Another,		/* CMOV_GdEd		*/
+    /* 0F 48 */ Another,		/* CMOV_GdEd		*/
+    /* 0F 49 */ Another,		/* CMOV_GdEd		*/
+    /* 0F 4A */ Another,		/* CMOV_GdEd		*/
+    /* 0F 4B */ Another,		/* CMOV_GdEd		*/
+    /* 0F 4C */ Another,		/* CMOV_GdEd		*/
+    /* 0F 4D */ Another,		/* CMOV_GdEd		*/
+    /* 0F 4E */ Another,		/* CMOV_GdEd		*/
+    /* 0F 4F */ Another,		/* CMOV_GdEd		*/
+    /* 0F 50 */ InvalidOpcode,
+    /* 0F 51 */ InvalidOpcode,
+    /* 0F 52 */ InvalidOpcode,
+    /* 0F 53 */ InvalidOpcode,
+    /* 0F 54 */ InvalidOpcode,
+    /* 0F 55 */ InvalidOpcode,
+    /* 0F 56 */ InvalidOpcode,
+    /* 0F 57 */ InvalidOpcode,
+    /* 0F 58 */ InvalidOpcode,
+    /* 0F 59 */ InvalidOpcode,
+    /* 0F 5A */ InvalidOpcode,
+    /* 0F 5B */ InvalidOpcode,
+    /* 0F 5C */ InvalidOpcode,
+    /* 0F 5D */ InvalidOpcode,
+    /* 0F 5E */ InvalidOpcode,
+    /* 0F 5F */ InvalidOpcode,
+    /* 0F 60 */ InvalidOpcode,
+    /* 0F 61 */ InvalidOpcode,
+    /* 0F 62 */ InvalidOpcode,
+    /* 0F 63 */ InvalidOpcode,
+    /* 0F 64 */ InvalidOpcode,
+    /* 0F 65 */ InvalidOpcode,
+    /* 0F 66 */ InvalidOpcode,
+    /* 0F 67 */ InvalidOpcode,
+    /* 0F 68 */ InvalidOpcode,
+    /* 0F 69 */ InvalidOpcode,
+    /* 0F 6A */ InvalidOpcode,
+    /* 0F 6B */ InvalidOpcode,
+    /* 0F 6C */ InvalidOpcode,
+    /* 0F 6D */ InvalidOpcode,
+    /* 0F 6E */ InvalidOpcode,
+    /* 0F 6F */ InvalidOpcode,
+    /* 0F 70 */ InvalidOpcode,
+    /* 0F 71 */ InvalidOpcode,
+    /* 0F 72 */ InvalidOpcode,
+    /* 0F 73 */ InvalidOpcode,
+    /* 0F 74 */ InvalidOpcode,
+    /* 0F 75 */ InvalidOpcode,
+    /* 0F 76 */ InvalidOpcode,
+    /* 0F 77 */ InvalidOpcode,
+    /* 0F 78 */ InvalidOpcode,
+    /* 0F 79 */ InvalidOpcode,
+    /* 0F 7A */ InvalidOpcode,
+    /* 0F 7B */ InvalidOpcode,
+    /* 0F 7C */ InvalidOpcode,
+    /* 0F 7D */ InvalidOpcode,
+    /* 0F 7E */ InvalidOpcode,
+    /* 0F 7F */ InvalidOpcode,
+    /* 0F 80 */ Immediate_BrOff32,	/* JCC_Jd		*/
+    /* 0F 81 */ Immediate_BrOff32,	/* JCC_Jd		*/
+    /* 0F 82 */ Immediate_BrOff32,	/* JCC_Jd		*/
+    /* 0F 83 */ Immediate_BrOff32,	/* JCC_Jd		*/
+    /* 0F 84 */ Immediate_BrOff32,	/* JCC_Jd		*/
+    /* 0F 85 */ Immediate_BrOff32,	/* JCC_Jd		*/
+    /* 0F 86 */ Immediate_BrOff32,	/* JCC_Jd		*/
+    /* 0F 87 */ Immediate_BrOff32,	/* JCC_Jd		*/
+    /* 0F 88 */ Immediate_BrOff32,	/* JCC_Jd		*/
+    /* 0F 89 */ Immediate_BrOff32,	/* JCC_Jd		*/
+    /* 0F 8A */ Immediate_BrOff32,	/* JCC_Jd		*/
+    /* 0F 8B */ Immediate_BrOff32,	/* JCC_Jd		*/
+    /* 0F 8C */ Immediate_BrOff32,	/* JCC_Jd		*/
+    /* 0F 8D */ Immediate_BrOff32,	/* JCC_Jd		*/
+    /* 0F 8E */ Immediate_BrOff32,	/* JCC_Jd		*/
+    /* 0F 8F */ Immediate_BrOff32,	/* JCC_Jd		*/
+    /* 0F 90 */ Another,		/* SETO_Eb		*/
+    /* 0F 91 */ Another,		/* SETNO_Eb		*/
+    /* 0F 92 */ Another,		/* SETB_Eb		*/
+    /* 0F 93 */ Another,		/* SETNB_Eb		*/
+    /* 0F 94 */ Another,		/* SETZ_Eb		*/
+    /* 0F 95 */ Another,		/* SETNZ_Eb		*/
+    /* 0F 96 */ Another,		/* SETBE_Eb		*/
+    /* 0F 97 */ Another,		/* SETNBE_Eb		*/
+    /* 0F 98 */ Another,		/* SETS_Eb		*/
+    /* 0F 99 */ Another,		/* SETNS_Eb		*/
+    /* 0F 9A */ Another,		/* SETP_Eb		*/
+    /* 0F 9B */ Another,		/* SETNP_Eb		*/
+    /* 0F 9C */ Another,		/* SETL_Eb		*/
+    /* 0F 9D */ Another,		/* SETNL_Eb		*/
+    /* 0F 9E */ Another,		/* SETLE_Eb		*/
+    /* 0F 9F */ Another,		/* SETNLE_Eb		*/
+    /* 0F A0 */ 0,			/* PUSH_FS		*/
+    /* 0F A1 */ 0,			/* POP_FS		*/
+    /* 0F A2 */ 0,			/* CPUID		*/
+    /* 0F A3 */ Another,		/* BT_EvGv		*/
+    /* 0F A4 */ Another | Immediate_Ib,	/* SHLD_EdGd		*/
+    /* 0F A5 */ Another,		/* SHLD_EdGd		*/
+    /* 0F A6 */ 0,			/* CMPXCHG_XBTS		*/
+    /* 0F A7 */ 0,			/* CMPXCHG_IBTS		*/
+    /* 0F A8 */ 0,			/* PUSH_GS		*/
+    /* 0F A9 */ 0,			/* POP_GS		*/
+    /* 0F AA */ 0,			/* RSM			*/
+    /* 0F AB */ Another,		/* BTS_EvGv		*/
+    /* 0F AC */ Another | Immediate_Ib,	/* SHRD_EdGd		*/
+    /* 0F AD */ Another,		/* SHRD_EdGd		*/
+    /* 0F AE */ InvalidOpcode,
+    /* 0F AF */ Another,		/* IMUL_GdEd		*/
+    /* 0F B0 */ Another,		/* CMPXCHG_EbGb		*/
+    /* 0F B1 */ Another,		/* CMPXCHG_EdGd		*/
+    /* 0F B2 */ Another,		/* LSS_GvMp		*/
+    /* 0F B3 */ Another,		/* BTR_EvGv		*/
+    /* 0F B4 */ Another,		/* LFS_GvMp		*/
+    /* 0F B5 */ Another,		/* LGS_GvMp		*/
+    /* 0F B6 */ Another,		/* MOVZX_GdEb		*/
+    /* 0F B7 */ Another,		/* MOVZX_GdEw		*/
+    /* 0F B8 */ InvalidOpcode,
+    /* 0F B9 */ InvalidOpcode,
+    /* 0F BA */ Another | GroupN | PutGroupIndex (G8EvIb),
+    /* 0F BB */ Another,		/* BTC_EvGv		*/
+    /* 0F BC */ Another,		/* BSF_GvEv		*/
+    /* 0F BD */ Another,		/* BSR_GvEv		*/
+    /* 0F BE */ Another,		/* MOVSX_GdEb		*/
+    /* 0F BF */ Another,		/* MOVSX_GdEw		*/
+    /* 0F C0 */ Another,		/* XADD_EbGb		*/
+    /* 0F C1 */ Another,		/* XADD_EdGd		*/
+    /* 0F C2 */ InvalidOpcode,
+    /* 0F C3 */ InvalidOpcode,
+    /* 0F C4 */ InvalidOpcode,
+    /* 0F C5 */ InvalidOpcode,
+    /* 0F C6 */ InvalidOpcode,
+    /* 0F C7 */ Another | GroupN | PutGroupIndex (G9),
+    /* 0F C8 */ 0,			/* BSWAP_EAX		*/
+    /* 0F C9 */ 0,			/* BSWAP_ECX		*/
+    /* 0F CA */ 0,			/* BSWAP_EDX		*/
+    /* 0F CB */ 0,			/* BSWAP_EBX		*/
+    /* 0F CC */ 0,			/* BSWAP_ESP		*/
+    /* 0F CD */ 0,			/* BSWAP_EBP		*/
+    /* 0F CE */ 0,			/* BSWAP_ESI		*/
+    /* 0F CF */ 0,			/* BSWAP_EDI		*/
+    /* 0F D0 */ InvalidOpcode,
+    /* 0F D1 */ InvalidOpcode,
+    /* 0F D2 */ InvalidOpcode,
+    /* 0F D3 */ InvalidOpcode,
+    /* 0F D4 */ InvalidOpcode,
+    /* 0F D5 */ InvalidOpcode,
+    /* 0F D6 */ InvalidOpcode,
+    /* 0F D7 */ InvalidOpcode,
+    /* 0F D8 */ InvalidOpcode,
+    /* 0F D9 */ InvalidOpcode,
+    /* 0F DA */ InvalidOpcode,
+    /* 0F DB */ InvalidOpcode,
+    /* 0F DC */ InvalidOpcode,
+    /* 0F DD */ InvalidOpcode,
+    /* 0F DE */ InvalidOpcode,
+    /* 0F DF */ InvalidOpcode,
+    /* 0F E0 */ InvalidOpcode,
+    /* 0F E1 */ InvalidOpcode,
+    /* 0F E2 */ InvalidOpcode,
+    /* 0F E3 */ InvalidOpcode,
+    /* 0F E4 */ InvalidOpcode,
+    /* 0F E5 */ InvalidOpcode,
+    /* 0F E6 */ InvalidOpcode,
+    /* 0F E7 */ InvalidOpcode,
+    /* 0F E8 */ InvalidOpcode,
+    /* 0F E9 */ InvalidOpcode,
+    /* 0F EA */ InvalidOpcode,
+    /* 0F EB */ InvalidOpcode,
+    /* 0F EC */ InvalidOpcode,
+    /* 0F ED */ InvalidOpcode,
+    /* 0F EE */ InvalidOpcode,
+    /* 0F EF */ InvalidOpcode,
+    /* 0F F0 */ InvalidOpcode,
+    /* 0F F1 */ InvalidOpcode,
+    /* 0F F2 */ InvalidOpcode,
+    /* 0F F3 */ InvalidOpcode,
+    /* 0F F4 */ InvalidOpcode,
+    /* 0F F5 */ InvalidOpcode,
+    /* 0F F6 */ InvalidOpcode,
+    /* 0F F7 */ InvalidOpcode,
+    /* 0F F8 */ InvalidOpcode,
+    /* 0F F9 */ InvalidOpcode,
+    /* 0F FA */ InvalidOpcode,
+    /* 0F FB */ InvalidOpcode,
+    /* 0F FC */ InvalidOpcode,
+    /* 0F FD */ InvalidOpcode,
+    /* 0F FE */ InvalidOpcode,
+    /* 0F FF */ InvalidOpcode,
+};
+
+
+
+unsigned
+fetchDecode (Bit8u * iptr, instruction_t * instruction,
+	     unsigned remain, Boolean is_32)
+{
+/* remain must be at least 1 */
+
+    unsigned b1, b2, ilen = 1, attr;
+    unsigned imm_mode, offset;
+    unsigned rm;
+
+    instruction->os_32 = instruction->as_32 = is_32;
+//  instruction->ResolveModrm = NULL;
+    instruction->seg = SEG_REG_NULL;
+    instruction->rep_used = 0;
+
+  fetch_b1:
+    b1 = *iptr++;
+
+  another_byte:
+    offset = instruction->os_32 << 9;	/* multiply by 512 */
+
+    instruction->attr = attr = OpcodeInfo[b1 + offset];
+
+    if (attr & Another)
+    {
+	if (attr & Prefix)
+	{
+	    switch (b1)
+	    {
+	    case 0x66:		/* OpSize		*/
+
+		instruction->os_32 = !is_32;
+		if (ilen < remain)
+		{
+		    ilen++;
+		    goto fetch_b1;
+		}
+		return (0);
+
+	    case 0x67:		/* AddrSize		*/
+
+		instruction->as_32 = !is_32;
+		if (ilen < remain)
+		{
+		    ilen++;
+		    goto fetch_b1;
+		}
+		return (0);
+
+	    case 0xf2:		/* REPNE/REPNZ		*/
+	    case 0xf3:		/* REP/REPE/REPZ	*/
+
+		instruction->rep_used = b1;
+		if (ilen < remain)
+		{
+		    ilen++;
+		    goto fetch_b1;
+		}
+		return (0);
+		break;
+
+	    case 0x2e:		/* CS:			*/
+
+		instruction->seg = SEG_REG_CS;
+		ilen++;
+		goto fetch_b1;
+		break;
+
+	    case 0x26:		/* ES:			*/
+
+		instruction->seg = SEG_REG_ES;
+		ilen++;
+		goto fetch_b1;
+		break;
+
+	    case 0x36:		/* SS:			*/
+
+		instruction->seg = SEG_REG_SS;
+		ilen++;
+		goto fetch_b1;
+		break;
+
+	    case 0x3e:		/* DS:			*/
+
+		instruction->seg = SEG_REG_DS;
+		ilen++;
+		goto fetch_b1;
+		break;
+
+	    case 0x64:		/* FS:			*/
+
+		instruction->seg = SEG_REG_FS;
+		ilen++;
+		goto fetch_b1;
+		break;
+
+	    case 0x65:		/* GS:			*/
+
+		instruction->seg = SEG_REG_GS;
+		ilen++;
+		goto fetch_b1;
+		break;
+
+	    case 0xf0:		/* LOCK:		*/
+
+		ilen++;
+		goto fetch_b1;
+		break;
+
+	    default:
+		return (0);
+
+		/* panic("fetch_decode: prefix default = 0x%02x\n", b1); */
+	    }
+	}
+
+	/* opcode requires another byte */
+
+	if (ilen < remain)
+	{
+	    ilen++;
+	    b2 = *iptr++;
+	    if (b1 == 0x0f)
+	    {
+		/* 2-byte prefix */
+		b1 = 0x100 | b2;
+		goto another_byte;
+	    }
+	}
+	else
+	    return (0);
+
+	/* Parse mod-nnn-rm and related bytes */
+
+	instruction->modrm = b2;
+	rm = instruction->rm = b2 & 0x07;
+	instruction->mod = b2 & 0xc0;	/* leave unshifted 	*/
+
+	instruction->nnn = (b2 >> 3) & 0x07;
+
+	if (instruction->mod == 0xc0)	/* mod == 11b		*/
+	{
+
+	    goto modrm_done;
+	}
+
+	if (instruction->as_32)		/* 32-bit addressing modes; note    */
+	{				/* note that mod==11b handled above */
+	    if (rm != 4)		/* no s-i-b byte		    */
+	    {
+		if (instruction->mod == 0x00)
+		{			/* mod == 00b		*/
+//		    instruction->ResolveModrm = BxResolve32Mod0[rm];
+
+		    if (NULL_SEG_REG (instruction->seg))
+			instruction->seg = SEG_REG_DS;
+
+		    if (rm == 5)
+		    {
+			if ((ilen + 3) < remain)
+			{
+			    Bit32u imm32u;
+
+			    imm32u = *iptr++;
+			    imm32u |= (*iptr++) << 8;
+			    imm32u |= (*iptr++) << 16;
+			    imm32u |= (*iptr++) << 24;
+			    instruction->rm_addr = imm32u;
+			    ilen += 4;
+			    goto modrm_done;
+			}
+			else
+			{
+			    return (0);
+			}
+		    }
+
+		    /* mod==00b, rm!=4, rm!=5 */
+		    goto modrm_done;
+		}
+
+		if (instruction->mod == 0x40)
+		{			/* mod == 01b		*/
+//		    instruction->ResolveModrm = BxResolve32Mod1or2[rm];
+
+		    if (NULL_SEG_REG (instruction->seg))
+			instruction->seg = sreg_mod01_rm32[rm];
+
+		  get_8bit_displ:
+		    if (ilen < remain)
+		    {
+			/* 8 sign extended to 32 */
+			instruction->displ32u = (Bit8s) * iptr++;
+			ilen++;
+			goto modrm_done;
+		    }
+		    else
+		    {
+			return (0);
+		    }
+		}
+
+		/* (mod == 0x80) mod == 10b */
+
+//		instruction->ResolveModrm = BxResolve32Mod1or2[rm];
+
+		if (NULL_SEG_REG (instruction->seg))
+		    instruction->seg = sreg_mod10_rm32[rm];
+
+	      get_32bit_displ:
+		if ((ilen + 3) < remain)
+		{
+		    Bit32u imm32u;
+
+		    imm32u = *iptr++;
+		    imm32u |= (*iptr++) << 8;
+		    imm32u |= (*iptr++) << 16;
+		    imm32u |= (*iptr++) << 24;
+		    instruction->displ32u = imm32u;
+		    ilen += 4;
+		    goto modrm_done;
+		}
+		else
+		{
+		    return (0);
+		}
+	    }
+	    else
+	    {			/* mod!=11b, rm==4, s-i-b byte follows	*/
+		unsigned sib, base;
+
+		if (ilen < remain)
+		{
+		    sib = *iptr++;
+		    ilen++;
+		}
+		else
+		{
+		    return (0);
+		}
+
+		instruction->sib = sib;
+		base = instruction->base = sib & 0x07;
+		sib >>= 3;
+		instruction->index = sib & 0x07;
+		sib >>= 3;
+		instruction->scale = sib;
+
+		if (instruction->mod == 0x00)
+		{		/* mod==00b, rm==4	*/
+//		    instruction->ResolveModrm = BxResolve32Mod0Base[base];
+
+		    if (NULL_SEG_REG (instruction->seg))
+			instruction->seg = sreg_mod0_base32[base];
+
+		    if (instruction->base == 0x05)
+		    {
+			goto get_32bit_displ;
+		    }
+
+		    /* mod==00b, rm==4, base!=5 */
+		    goto modrm_done;
+		}
+
+		if (instruction->mod == 0x40)
+		{		/* mod==01b, rm==4	*/
+//		    instruction->ResolveModrm = BxResolve32Mod1or2Base[base];
+
+		    if (NULL_SEG_REG (instruction->seg))
+			instruction->seg = sreg_mod1or2_base32[base];
+
+		    goto get_8bit_displ;
+		}
+
+		/* (instruction->mod == 0x80),  mod==10b, rm==4 */
+
+//		instruction->ResolveModrm = BxResolve32Mod1or2Base[base];
+
+		if (NULL_SEG_REG (instruction->seg))
+		    instruction->seg = sreg_mod1or2_base32[base];
+
+		goto get_32bit_displ;
+	    }
+	}
+	else	/* 16-bit addressing modes, mod==11b handled above */
+	{
+	    if (instruction->mod == 0x40)
+	    {			/* mod == 01b		*/
+//		instruction->ResolveModrm = BxResolve16Mod1or2[rm];
+
+		if (NULL_SEG_REG (instruction->seg))
+		    instruction->seg = sreg_mod01_rm16[rm];
+
+		if (ilen < remain)	/* 8 sign extended to 16 */
+		{
+		    instruction->displ16u = (Bit8s) * iptr++;
+		    ilen++;
+		    goto modrm_done;
+		}
+		else
+		{
+		    return (0);
+		}
+	    }
+
+	    if (instruction->mod == 0x80)
+	    {			/* mod == 10b		*/
+//		instruction->ResolveModrm = BxResolve16Mod1or2[rm];
+
+		if (NULL_SEG_REG (instruction->seg))
+		    instruction->seg = sreg_mod10_rm16[rm];
+
+		if ((ilen + 1) < remain)
+		{
+		    Bit16u displ16u;
+
+		    displ16u = *iptr++;
+		    displ16u |= (*iptr++) << 8;
+		    instruction->displ16u = displ16u;
+		    ilen += 2;
+		    goto modrm_done;
+		}
+		else
+		{
+		    return (0);
+		}
+	    }
+
+	    /* mod must be 00b at this point */
+
+//	    instruction->ResolveModrm = BxResolve16Mod0[rm];
+
+	    if (NULL_SEG_REG (instruction->seg))
+		instruction->seg = sreg_mod00_rm16[rm];
+
+	    if (rm == 0x06)
+	    {
+		if ((ilen + 1) < remain)
+		{
+		    Bit16u displ16u;
+
+		    displ16u = *iptr++;
+		    displ16u |= (*iptr++) << 8;
+		    instruction->rm_addr = displ16u;
+		    ilen += 2;
+		    goto modrm_done;
+		}
+		else
+		{
+		    return (0);
+		}
+	    }
+
+	    /* mod=00b rm!=6	*/
+	}
+
+      modrm_done:
+	if (attr & GroupN)
+	{
+	    /* There may be additional attributes in the individual	*/
+	    /* entry for a particular group.  Combine with those.	*/
+
+	    attr |= groupNattr[GetGroupIndex (attr)][instruction->nnn];
+	    instruction->attr = attr;
+	}
+	else
+	{
+	}
     }
-  else {
-    // Opcode does not require a MODRM byte.
-    // Note that a 2-byte opcode (0F XX) will jump to before
-    // the if() above after fetching the 2nd byte, so this path is
-    // taken in all cases if a modrm byte is NOT required.
+    else
+    {
+	/*
+	 *  Opcode does not require a MODRM byte.
+	 *  Note that a 2-byte opcode (0F XX) will jump to before
+	 *  the if() above after fetching the 2nd byte, so this path is
+	 *  taken in all cases if a modrm byte is NOT required.
+	 */
     }
 
+    imm_mode = attr & Immediate;
 
-  imm_mode = attr & Immediate;
+    if (imm_mode)
+    {
+	switch (imm_mode)
+	{
+	case Immediate_Ib:
+
+	    if (ilen < remain)
+	    {
+		instruction->Ib = *iptr;
+		ilen++;
+	    }
+	    else
+	    {
+		return (0);
+	    }
+
+	    break;
+
+	case Immediate_Ib_SE:	/* Sign extend to OS size	*/
+
+	    if (ilen < remain)
+	    {
+		Bit8s temp8s;
+
+		temp8s = *iptr;
+		if (instruction->os_32)
+		    instruction->Id = (Bit32s) temp8s;
+		else
+		    instruction->Iw = (Bit16s) temp8s;
+		ilen++;
+	    }
+	    else
+	    {
+		return (0);
+	    }
+
+	    break;
+
+	case Immediate_BrOff32:
+	case Immediate_Iv:
+	case Immediate_IvIw:	/* CALL_Ap			*/
+
+	    if (instruction->os_32)
+	    {
+		if ((ilen + 3) < remain)
+		{
+		    Bit32u imm32u;
+
+		    imm32u = *iptr++;
+		    imm32u |= (*iptr++) << 8;
+		    imm32u |= (*iptr++) << 16;
+		    imm32u |= (*iptr) << 24;
+		    instruction->Id = imm32u;
+		    ilen += 4;
+		}
+		else
+		{
+		    return (0);
+		}
+	    }
+	    else
+	    {
+		if ((ilen + 1) < remain)
+		{
+		    Bit16u imm16u;
+
+		    imm16u = *iptr++;
+		    imm16u |= (*iptr) << 8;
+		    instruction->Iw = imm16u;
+		    ilen += 2;
+		}
+		else
+		{
+		    return (0);
+		}
+	    }
+
+	    if (imm_mode != Immediate_IvIw)
+		break;
+	    iptr++;
+
+	    /* Get Iw for Immediate_IvIw */
+
+	    if ((ilen + 1) < remain)
+	    {
+		Bit16u imm16u;
+
+		imm16u = *iptr++;
+		imm16u |= (*iptr) << 8;
+		instruction->Iw2 = imm16u;
+		ilen += 2;
+	    }
+	    else
+	    {
+		return (0);
+	    }
+
+	    break;
+
+	case Immediate_O:
+
+	    if (instruction->as_32)
+	    {
+		/* fetch 32bit address into Id */
+
+		if ((ilen + 3) < remain)
+		{
+		    Bit32u imm32u;
+
+		    imm32u = *iptr++;
+		    imm32u |= (*iptr++) << 8;
+		    imm32u |= (*iptr++) << 16;
+		    imm32u |= (*iptr) << 24;
+		    instruction->Id = imm32u;
+		    ilen += 4;
+		}
+		else
+		{
+		    return (0);
+		}
+	    }
+	    else
+	    {
+		/* fetch 16bit address into Id */
+
+		if ((ilen + 1) < remain)
+		{
+		    Bit32u imm32u;
+
+		    imm32u = *iptr++;
+		    imm32u |= (*iptr) << 8;
+		    instruction->Id = imm32u;
+		    ilen += 2;
+		}
+		else
+		{
+		    return (0);
+		}
+	    }
+
+	    break;
+
+	case Immediate_Iw:
+	case Immediate_IwIb:
+
+	    if ((ilen + 1) < remain)
+	    {
+		Bit16u imm16u;
+
+		imm16u = *iptr++;
+		imm16u |= (*iptr) << 8;
+		instruction->Iw = imm16u;
+		ilen += 2;
+	    }
+	    else
+	    {
+		return (0);
+	    }
+
+	    if (imm_mode == Immediate_Iw)
+		break;
+
+	    iptr++;
+
+	    if (ilen < remain)
+	    {
+		instruction->Ib2 = *iptr;
+		ilen++;
+	    }
+	    else
+	    {
+		return (0);
+	    }
+
+	    break;
+
+	case Immediate_BrOff8:
+
+	    if (ilen < remain)
+	    {
+		Bit8s temp8s;
+
+		temp8s = *iptr;
+		instruction->Id = temp8s;
+		ilen++;
+	    }
+	    else
+	    {
+		return (0);
+	    }
+
+	    break;
+
+	case Immediate_BrOff16:
+
+	    if ((ilen + 1) < remain)
+	    {
+		Bit16u imm16u;
+
+		imm16u = *iptr++;
+		imm16u |= (*iptr) << 8;
+		instruction->Id = (Bit16s) imm16u;
+		ilen += 2;
+	    }
+	    else
+	    {
+		return (0);
+	    }
+
+	    break;
 
-  if (imm_mode) {
-    switch (imm_mode) {
-      case Immediate_Ib:
-        if (ilen < remain) {
-          instruction->Ib = *iptr;
-          ilen++;
-          }
-        else {
-          return(0);
-          }
-        break;
-      case Immediate_Ib_SE: // Sign extend to OS size
-        if (ilen < remain) {
-          Bit8s temp8s;
-          temp8s = *iptr;
-          if (instruction->os_32)
-            instruction->Id = (Bit32s) temp8s;
-          else
-            instruction->Iw = (Bit16s) temp8s;
-          ilen++;
-          }
-        else {
-          return(0);
-          }
-        break;
-      case Immediate_BrOff32:
-      case Immediate_Iv:
-      case Immediate_IvIw: // CALL_Ap
-        if (instruction->os_32) {
-          if ((ilen+3) < remain) {
-            Bit32u imm32u;
-            imm32u = *iptr++;
-            imm32u |= (*iptr++) << 8;
-            imm32u |= (*iptr++) << 16;
-            imm32u |= (*iptr) << 24;
-            instruction->Id = imm32u;
-            ilen += 4;
-            }
-          else {
-            return(0);
-            }
-          }
-        else {
-          if ((ilen+1) < remain) {
-            Bit16u imm16u;
-            imm16u = *iptr++;
-            imm16u |= (*iptr) << 8;
-            instruction->Iw = imm16u;
-            ilen += 2;
-            }
-          else {
-            return(0);
-            }
-          }
-        if (imm_mode != Immediate_IvIw)
-          break;
-        iptr++;
-        // Get Iw for Immediate_IvIw
-        if ((ilen+1) < remain) {
-          Bit16u imm16u;
-          imm16u = *iptr++;
-          imm16u |= (*iptr) << 8;
-          instruction->Iw2 = imm16u;
-          ilen += 2;
-          }
-        else {
-          return(0);
-          }
-        break;
-      case Immediate_O:
-        if (instruction->as_32) {
-          // fetch 32bit address into Id
-          if ((ilen+3) < remain) {
-            Bit32u imm32u;
-            imm32u = *iptr++;
-            imm32u |= (*iptr++) << 8;
-            imm32u |= (*iptr++) << 16;
-            imm32u |= (*iptr) << 24;
-            instruction->Id = imm32u;
-            ilen += 4;
-            }
-          else {
-            return(0);
-            }
-          }
-        else {
-          // fetch 16bit address into Id
-          if ((ilen+1) < remain) {
-            Bit32u imm32u;
-            imm32u = *iptr++;
-            imm32u |= (*iptr) << 8;
-            instruction->Id = imm32u;
-            ilen += 2;
-            }
-          else {
-            return(0);
-            }
-          }
-        break;
-      case Immediate_Iw:
-      case Immediate_IwIb:
-        if ((ilen+1) < remain) {
-          Bit16u imm16u;
-          imm16u = *iptr++;
-          imm16u |= (*iptr) << 8;
-          instruction->Iw = imm16u;
-          ilen += 2;
-          }
-        else {
-          return(0);
-          }
-        if (imm_mode == Immediate_Iw) break;
-        iptr++;
-        if (ilen < remain) {
-          instruction->Ib2 = *iptr;
-          ilen++;
-          }
-        else {
-          return(0);
-          }
-        break;
-      case Immediate_BrOff8:
-        if (ilen < remain) {
-          Bit8s temp8s;
-          temp8s = *iptr;
-          instruction->Id = temp8s;
-          ilen++;
-          }
-        else {
-          return(0);
-          }
-        break;
-      case Immediate_BrOff16:
-        if ((ilen+1) < remain) {
-          Bit16u imm16u;
-          imm16u = *iptr++;
-          imm16u |= (*iptr) << 8;
-          instruction->Id = (Bit16s) imm16u;
-          ilen += 2;
-          }
-        else {
-          return(0);
-          }
-        break;
-      default:
-//printf("b1 was %x\n", b1);
-        return(0);
-        //panic("fetchdecode: imm_mode = %u\n", imm_mode);
-      }
-    }
+	default:
 
+//	    printf("b1 was %x\n", b1);
+	    return (0);
+
+	    /* panic("fetchdecode: imm_mode = %u\n", imm_mode); */
+	}
+    }
 
-  instruction->b1 = b1;
-  instruction->ilen = ilen;
-  return(1);
+    instruction->b1 = b1;
+    instruction->ilen = ilen;
+    return (1);
 }
diff -Nur plex86-old/kernel/monitor.c plex86/kernel/monitor.c
--- plex86-old/kernel/monitor.c	Tue Mar 28 12:59:04 2000
+++ plex86/kernel/monitor.c	Sat Apr  1 15:49:57 2000
@@ -36,6 +36,7 @@
 static void map_nexus_pages(Bit32u *, unsigned, Bit32u *, page_t *);
 static void map_monitor(vm_t *vm);
 static void virtualize_guest_paging(vm_t *vm);
+
 #ifdef SBE
 static void sbe_setup(vm_t *vm);
 #endif
@@ -44,26 +45,27 @@
 #define IDT_EXCEPTION_ERROR    1
 #define IDT_EXCEPTION_NOERROR  2
 
-// Access to label offsets in nexus.S...
-// From the host address perspective
+/* Access to label offsets in nexus.S... From the host address perspective */
 #define HOST_NEXUS_OFFSET(field) \
-  ((Bit32u)vm->host.addr.nexus + (((Bit32u) &field) - ((Bit32u) &__nexus_start)))
+    ((Bit32u)vm->host.addr.nexus + (((Bit32u) &field) - ((Bit32u) &__nexus_start)))
 
-// From the monitor/guest address perspective.
+/* From the monitor/guest address perspective. */
 #define MON_NEXUS_OFFSET(field) \
-  (((Bit32u)vm->guest.addr.nexus) + (((Bit32u) &field) - ((Bit32u) &__nexus_start)))
+    (((Bit32u)vm->guest.addr.nexus) + (((Bit32u) &field) - ((Bit32u) &__nexus_start)))
 
 
-// We need to set the monitor CS/DS base address so that the module pages,
-// which are mapped starting at linear address 'laddr' into the guest address 
-// space, reside at the same offset relative to the monitor CS base as they 
-// reside relative to the kernel CS base in the host address space.  This way,
-// we can execute the (non-relocatable) module code within the guest address 
-// space ...
+/*
+ *  We need to set the monitor CS/DS base address so that the module pages,
+ *  which are mapped starting at linear address 'laddr' into the guest address 
+ *  space, reside at the same offset relative to the monitor CS base as they 
+ *  reside relative to the kernel CS base in the host address space.  This way,
+ *  we can execute the (non-relocatable) module code within the guest address 
+ *  space ...
+ */
 #define MON_BASE_FROM_LADDR(laddr) \
-  ((laddr) - (monitor_pages.start_addr & ~0xfff))
+    ((laddr) - (monitor_pages.start_addr & ~0xfff))
 #define LADDR_FROM_MON_BASE(base) \
-  ((base) + (monitor_pages.start_addr & ~0xfff))
+    ((base) + (monitor_pages.start_addr & ~0xfff))
 
 opcode_vmap_t opcode_vmap2;
 
@@ -72,7 +74,7 @@
 /* Helper routines                                                      */
 /************************************************************************/
 
-  void
+void
 zero_memory(void *ptr, int size)
 {
     char *p = ptr;
@@ -80,7 +82,7 @@
         *p++ = 0;
 }
 
-  void
+void
 copy_memory(void *dst, void *src, int size)
 {
     char *d = dst;
@@ -94,7 +96,7 @@
 /* Main monitor code                                                    */
 /************************************************************************/
 
-  int
+int
 init_monitor(vm_t *vm)
 /*
  *  init_monitor():  Initialise the monitor context.
@@ -106,7 +108,7 @@
  *     none
  */
 {
-    // These variables are used to set up the monitor pagetables
+    /* These variables are used to set up the monitor pagetables */
     unsigned pdi, pti;
     unsigned int i;
     Bit32u nexus_size;
@@ -114,20 +116,20 @@
     Bit32u laddr, base;
     int r;
 
-// +++
-opcode_vmap2 = opcode_vmap;
-opcode_vmap2.standard[0x90] = 0; // virtualize NOP
-opcode_vmap2.standard[0x16] = OpcodeRunNative;
-opcode_vmap2.standard[0x1f] = OpcodeRunNative;
 
-    vm->host.initialized = 0; // monitor not yet initialized.
+    /* +++ */
+    opcode_vmap2 = opcode_vmap;
+    opcode_vmap2.standard[0x90] = 0; /* virtualize NOP */
+    opcode_vmap2.standard[0x16] = OpcodeRunNative;
+    opcode_vmap2.standard[0x1f] = OpcodeRunNative;
 
-    // Start out using pointers in host space.
+    vm->host.initialized = 0; /* monitor not yet initialized. */
+
+    /* Start out using pointers in host space. */
     vm->common.addr = &vm->host.addr;
 
-    //
-    // Initialize nexus
-    //
+
+    /* Initialize nexus */
 
     zero_memory(vm->host.addr.nexus, 4096);
 
@@ -138,18 +140,16 @@
     copy_memory(vm->host.addr.nexus, &__nexus_start, nexus_size);
 
 
-    //
-    // Init the convenience pointers.
-    //
+    /* Init the convenience pointers. */
 
-    // Pointer to host2guest routine inside nexus page
+    /* Pointer to host2guest routine inside nexus page */
     vm->host.__host2guest = (void (*)(void)) HOST_NEXUS_OFFSET(__host2guest);
 
-    // Pointer to guest context on monitor stack
+    /* Pointer to guest context on monitor stack */
     vm->host.guest_context = (guest_context_t *)
       ((Bit32u)vm->host.addr.nexus + PAGESIZE - sizeof(guest_context_t));
 
-    // Zero out various monitor data structures
+    /* Zero out various monitor data structures */
     zero_memory(vm->host.addr.page_dir, 4096);
     zero_memory(vm->host.addr.idt, MON_IDT_SIZE);
     zero_memory(vm->host.addr.gdt, MON_GDT_SIZE);
@@ -160,51 +160,55 @@
     zero_memory(vm->common.page_usage, sizeof(vm->common.page_usage));
 
 
-    // ================
-    // Nexus Page Table
-    // ================
-
-    // All structures needed by the monitor inside the guest environment
-    // (code to perform the transition between host<-->guest, fault handler
-    // code, various processor data structures like page directory, GDT,
-    // IDT, TSS etc.) are mapped into a single Page Table.
-    //
-    // This allows us to migrate the complete nexus to anywhere in the
-    // guest address space by just updating a single (unused) page directory
-    // entry in the monitor/guest page directory to point to this nexus
-    // page table.
-    //
-    // To simplify nexus migration, we try to avoid storing guest linear
-    // addresses to nexus structures as far as possible.  Instead, we use
-    // offsets relative to the monitor code/data segments.  As we update
-    // the base of these segments whenever the monitor migrates, the net
-    // effect is that those *offsets* remain valid across nexus migration. 
+    /*
+     *  ================
+     *  Nexus Page Table
+     *  ================
+     *
+     *  All structures needed by the monitor inside the guest environment
+     *  (code to perform the transition between host<-->guest, fault handler
+     *  code, various processor data structures like page directory, GDT,
+     *  IDT, TSS etc.) are mapped into a single Page Table.
+     *
+     *  This allows us to migrate the complete nexus to anywhere in the
+     *  guest address space by just updating a single (unused) page directory
+     *  entry in the monitor/guest page directory to point to this nexus
+     *  page table.
+     *
+     *  To simplify nexus migration, we try to avoid storing guest linear
+     *  addresses to nexus structures as far as possible.  Instead, we use
+     *  offsets relative to the monitor code/data segments.  As we update
+     *  the base of these segments whenever the monitor migrates, the net
+     *  effect is that those *offsets* remain valid across nexus migration. 
+     */
 
-    // Fill in the PDE flags
+    /* Fill in the PDE flags */
     vm->host.nexus_pde.base = vm->common.pages.nexus_page_tbl;
     vm->host.nexus_pde.avail = 0;
-    vm->host.nexus_pde.G = 0;      // not global
-    vm->host.nexus_pde.PS = 0;     // 4K pages
-    vm->host.nexus_pde.D = 0;      // (unused in pde)
-    vm->host.nexus_pde.A = 0;      // not accessed
-    vm->host.nexus_pde.PCD = 0;    // normal caching
-    vm->host.nexus_pde.PWT = 0;    // normal write-back
-    vm->host.nexus_pde.US = 0;     // user *cannot* access
-    vm->host.nexus_pde.RW = 1;     // read or write
-    vm->host.nexus_pde.P = 1;      // present in memory
+    vm->host.nexus_pde.G = 0;      /* not global		*/
+    vm->host.nexus_pde.PS = 0;     /* 4K pages			*/
+    vm->host.nexus_pde.D = 0;      /* (unused in pde)		*/
+    vm->host.nexus_pde.A = 0;      /* not accessed		*/
+    vm->host.nexus_pde.PCD = 0;    /* normal caching		*/
+    vm->host.nexus_pde.PWT = 0;    /* normal write-back		*/
+    vm->host.nexus_pde.US = 0;     /* user *cannot* access	*/
+    vm->host.nexus_pde.RW = 1;     /* read or write		*/
+    vm->host.nexus_pde.P = 1;      /* present in memory		*/
 
-    // clear Page Table
+    /* clear Page Table */
     pageTable = vm->host.addr.nexus_page_tbl;
     zero_memory(pageTable, 4096);
 
-    // Map pages holding nexus structures into the nexus page table.
-    // For calculating the offsets, we pretend we're mapping the nexus
-    // page table at linear address zero.  As the offsets are invariant
-    // under nexus migration, this address is as good as any ;-)
+    /*
+     *  Map pages holding nexus structures into the nexus page table.
+     *  For calculating the offsets, we pretend we're mapping the nexus
+     *  page table at linear address zero.  As the offsets are invariant
+     *  under nexus migration, this address is as good as any ;-)
+     */
     laddr = 0;
     base = MON_BASE_FROM_LADDR(laddr);
 
-    //vm->host.addr.nexus->module_offset = laddr - base; // not needed
+//  vm->host.addr.nexus->module_offset = laddr - base; /* not needed */
     map_nexus_pages(monitor_pages.page, monitor_pages.n_pages, &laddr, pageTable);
 
     vm->guest.addr.nexus = (nexus_t *) (laddr - base);
@@ -233,84 +237,93 @@
     vm->guest.addr.page_dir = (pageEntry_t *) (laddr - base);
     map_nexus_pages(&vm->common.pages.page_dir, 1, &laddr, pageTable);
 
-    // Map virtualized guest page tables into guest memory.  This
-    // gives the nexus code the ability to modify the page mappings
-    // to implement the TLB trick.
+    /*
+     *  Map virtualized guest page tables into guest memory.  This
+     *  gives the nexus code the ability to modify the page mappings
+     *  to implement the TLB trick.
+     */
     virtualize_guest_paging(vm);
     vm->guest.addr.page_tbl = (page_t *) (laddr - base);
     map_nexus_pages(vm->common.pages.page_tbl, vm->common.pages.guest_n_megs>>2,
                     &laddr, pageTable);
 
-    // Map private code cache into guest memory.  This is needed
-    // by the scan-before-execute (prescan) logic, as we run code
-    // from private virtualized pages.
+    /*
+     *  Map private code cache into guest memory.  This is needed
+     *  by the scan-before-execute (prescan) logic, as we run code
+     *  from private virtualized pages.
+     */
     vm->guest.addr.icache = (page_t *) (laddr - base);
     map_nexus_pages(vm->common.pages.icache, 1, &laddr, pageTable);
 
-    // =====================
-    // Transition Page Table
-    // =====================
-
-    // To aid in the transition between host<-->monitor/guest spaces,
-    // we need to have an address identity map situation for at least
-    // one page; the page containing the transition code.   As we do
-    // not know in advance whether this linear address range is in use
-    // by the guest as well, we set aside a complete additional Page
-    // Table, which contains only a single PTE pointing to the nexus page.
-    //
-    // To create the identity map, we simply change the corresponding
-    // monitor page directory entry to point to this transition Page Table.
-    // This happens transparently inside the host<-->guest transition code; 
-    // both the guest/monitor code and the host side code never see this 
-    // transition page table entered into the page directory!
-    //
-    // NOTE: We need to ensure that the nexus page table never spans the
-    //       same 4Meg linear address space region as this page table!
-    //       As we are free to choose the nexus linear address, this is
-    //       not a problem.
 
-    // Get full linear address of nexus code page, as seen in host space.
+    /*
+     *  =====================
+     *  Transition Page Table
+     *  =====================
+     *
+     *  To aid in the transition between host<-->monitor/guest spaces,
+     *  we need to have an address identity map situation for at least
+     *  one page; the page containing the transition code.   As we do
+     *  not know in advance whether this linear address range is in use
+     *  by the guest as well, we set aside a complete additional Page
+     *  Table, which contains only a single PTE pointing to the nexus page.
+     *
+     *  To create the identity map, we simply change the corresponding
+     *  monitor page directory entry to point to this transition Page Table.
+     *  This happens transparently inside the host<-->guest transition code; 
+     *  both the guest/monitor code and the host side code never see this 
+     *  transition page table entered into the page directory!
+     *
+     *  NOTE: We need to ensure that the nexus page table never spans the
+     *        same 4Meg linear address space region as this page table!
+     *        As we are free to choose the nexus linear address, this is
+     *        not a problem.
+     */
+
+    /* Get full linear address of nexus code page, as seen in host space. */
     laddr = (Bit32u)vm->host.addr.nexus + vm->host.kernel_offset;
     pdi = laddr >> 22;
     pti = (laddr >> 12) & 0x3ff;
 
-    // We need to be able to access the PDE in the monitor page directory
-    // that corresponds to this linear address from both host and monitor 
-    // address spaces.
+    /*
+     *  We need to be able to access the PDE in the monitor page directory
+     *  that corresponds to this linear address from both host and monitor 
+     *  address spaces.
+     */
     vm->host.addr.nexus->transition_pde_p_host = vm->host.addr.page_dir + pdi;
     vm->host.addr.nexus->transition_pde_p_mon  = (pageEntry_t *)
                           (((Bit32u)vm->guest.addr.page_dir) + (pdi << 2));
     vm->host.addr.nexus->transition_laddr = laddr;
 
-    // Fill in the PDE flags
+    /* Fill in the PDE flags */
     vm->host.addr.nexus->transition_pde.base = vm->common.pages.transition_PT;
     vm->host.addr.nexus->transition_pde.avail = 0;
-    vm->host.addr.nexus->transition_pde.G = 0;      // not global
-    vm->host.addr.nexus->transition_pde.PS = 0;     // 4K pages
-    vm->host.addr.nexus->transition_pde.D = 0;      // (unused in pde)
-    vm->host.addr.nexus->transition_pde.A = 0;      // not accessed
-    vm->host.addr.nexus->transition_pde.PCD = 0;    // normal caching
-    vm->host.addr.nexus->transition_pde.PWT = 0;    // normal write-back
-    vm->host.addr.nexus->transition_pde.US = 0;     // user can not access
-    vm->host.addr.nexus->transition_pde.RW = 1;     // read or write
-    vm->host.addr.nexus->transition_pde.P = 1;      // present in memory
+    vm->host.addr.nexus->transition_pde.G = 0;      /* not global           */
+    vm->host.addr.nexus->transition_pde.PS = 0;     /* 4K pages             */
+    vm->host.addr.nexus->transition_pde.D = 0;      /* (unused in pde)      */
+    vm->host.addr.nexus->transition_pde.A = 0;      /* not accessed         */
+    vm->host.addr.nexus->transition_pde.PCD = 0;    /* normal caching       */
+    vm->host.addr.nexus->transition_pde.PWT = 0;    /* normal write-back    */
+    vm->host.addr.nexus->transition_pde.US = 0;     /* user can not access  */
+    vm->host.addr.nexus->transition_pde.RW = 1;     /* read or write        */
+    vm->host.addr.nexus->transition_pde.P = 1;      /* present in memory    */
 
-    // Clear Page Table; only one PTE is used.
+    /* Clear Page Table; only one PTE is used. */
     pageTable = vm->host.addr.transition_PT;
     zero_memory(pageTable, 4096);
 
-    // Fill in the PTE for identity mapping the code page
+    /* Fill in the PTE for identity mapping the code page */
     pageTable->u.pte[pti].base = vm->common.pages.nexus;
     pageTable->u.pte[pti].avail = 0;
-    pageTable->u.pte[pti].G = 0;      // not global
-    pageTable->u.pte[pti].PS = 0;     // (unused in pte)
-    pageTable->u.pte[pti].D = 0;      // clean
-    pageTable->u.pte[pti].A = 0;      // not accessed
-    pageTable->u.pte[pti].PCD = 0;    // normal caching
-    pageTable->u.pte[pti].PWT = 0;    // normal write-back
-    pageTable->u.pte[pti].US = 0;     // user can not access
-    pageTable->u.pte[pti].RW = 1;     // read or write
-    pageTable->u.pte[pti].P = 1;      // present in memory
+    pageTable->u.pte[pti].G = 0;      /* not global		*/
+    pageTable->u.pte[pti].PS = 0;     /* (unused in pte)	*/
+    pageTable->u.pte[pti].D = 0;      /* clean			*/
+    pageTable->u.pte[pti].A = 0;      /* not accessed		*/
+    pageTable->u.pte[pti].PCD = 0;    /* normal caching		*/
+    pageTable->u.pte[pti].PWT = 0;    /* normal write-back	*/
+    pageTable->u.pte[pti].US = 0;     /* user can not access	*/
+    pageTable->u.pte[pti].RW = 1;     /* read or write		*/
+    pageTable->u.pte[pti].P = 1;      /* present in memory	*/
 
 
     /* 
@@ -321,10 +334,10 @@
      *  stack and in a later stage, perhaps the I/O permission bitmap.
      */
 
-    // No task chain
+    /* No task chain */
     vm->host.addr.tss->back = 0;
 
-    // No debugging or I/O, for now
+    /* No debugging or I/O, for now */
     vm->host.addr.tss->trap = 0;
     vm->host.addr.tss->io = sizeof(tss_t);
 
@@ -334,25 +347,25 @@
      */
 
     r = 0;
-    r |= init_idt_slot(vm,  0, IDT_EXCEPTION_NOERROR); // Divide error
-    r |= init_idt_slot(vm,  1, IDT_EXCEPTION_NOERROR); // Debug exceptions
-    r |= init_idt_slot(vm,  2, IDT_INTERRUPT);         // NMI
-    r |= init_idt_slot(vm,  3, IDT_EXCEPTION_NOERROR); // Breakpoint
-    r |= init_idt_slot(vm,  4, IDT_EXCEPTION_NOERROR); // Overflow
-    r |= init_idt_slot(vm,  5, IDT_EXCEPTION_NOERROR); // Bounds check
-    r |= init_idt_slot(vm,  6, IDT_EXCEPTION_NOERROR); // Invalid opcode
-    r |= init_idt_slot(vm,  7, IDT_EXCEPTION_NOERROR); // FPU not available
-    r |= init_idt_slot(vm,  8, IDT_EXCEPTION_ERROR);   // Double fault
-    r |= init_idt_slot(vm,  9, IDT_EXCEPTION_NOERROR); // FPU segment overrun
-    r |= init_idt_slot(vm, 10, IDT_EXCEPTION_ERROR);   // Invalid TSS
-    r |= init_idt_slot(vm, 11, IDT_EXCEPTION_ERROR);   // Segment not present
-    r |= init_idt_slot(vm, 12, IDT_EXCEPTION_ERROR);   // Stack exception
-    r |= init_idt_slot(vm, 13, IDT_EXCEPTION_ERROR);   // GP fault
-    r |= init_idt_slot(vm, 14, IDT_EXCEPTION_ERROR);   // Page fault
-    r |= init_idt_slot(vm, 15, IDT_EXCEPTION_NOERROR); // reserved
-    r |= init_idt_slot(vm, 16, IDT_EXCEPTION_NOERROR); // Coprocessor error
-    r |= init_idt_slot(vm, 17, IDT_EXCEPTION_ERROR);   // Alignment check
-    r |= init_idt_slot(vm, 18, IDT_EXCEPTION_NOERROR); // Machine check
+    r |= init_idt_slot(vm,  0, IDT_EXCEPTION_NOERROR); /* Divide error        */
+    r |= init_idt_slot(vm,  1, IDT_EXCEPTION_NOERROR); /* Debug exceptions    */
+    r |= init_idt_slot(vm,  2, IDT_INTERRUPT);         /* NMI                 */
+    r |= init_idt_slot(vm,  3, IDT_EXCEPTION_NOERROR); /* Breakpoint          */
+    r |= init_idt_slot(vm,  4, IDT_EXCEPTION_NOERROR); /* Overflow            */
+    r |= init_idt_slot(vm,  5, IDT_EXCEPTION_NOERROR); /* Bounds check        */
+    r |= init_idt_slot(vm,  6, IDT_EXCEPTION_NOERROR); /* Invalid opcode      */
+    r |= init_idt_slot(vm,  7, IDT_EXCEPTION_NOERROR); /* FPU not available   */
+    r |= init_idt_slot(vm,  8, IDT_EXCEPTION_ERROR);   /* Double fault        */
+    r |= init_idt_slot(vm,  9, IDT_EXCEPTION_NOERROR); /* FPU segment overrun */
+    r |= init_idt_slot(vm, 10, IDT_EXCEPTION_ERROR);   /* Invalid TSS         */
+    r |= init_idt_slot(vm, 11, IDT_EXCEPTION_ERROR);   /* Segment not present */
+    r |= init_idt_slot(vm, 12, IDT_EXCEPTION_ERROR);   /* Stack exception     */
+    r |= init_idt_slot(vm, 13, IDT_EXCEPTION_ERROR);   /* GP fault            */
+    r |= init_idt_slot(vm, 14, IDT_EXCEPTION_ERROR);   /* Page fault          */
+    r |= init_idt_slot(vm, 15, IDT_EXCEPTION_NOERROR); /* reserved            */
+    r |= init_idt_slot(vm, 16, IDT_EXCEPTION_NOERROR); /* Coprocessor error   */
+    r |= init_idt_slot(vm, 17, IDT_EXCEPTION_ERROR);   /* Alignment check     */
+    r |= init_idt_slot(vm, 18, IDT_EXCEPTION_NOERROR); /* Machine check       */
 
     /* Reserved exceptions */
     for (i = 19; i < 32; i++)
@@ -393,18 +406,21 @@
 
     map_monitor(vm);
 
-    // +++ Really, we should call a routine here to determine which
-    // opcodes are available beyond the standard Pentium ones,
-    // and enhance structures in 'prescan.c' and 'fetchdecode.c'.
+    /*
+     *  +++ Really, we should call a routine here to determine which
+     *  opcodes are available beyond the standard Pentium ones,
+     *  and enhance structures in 'prescan.c' and 'fetchdecode.c'.
+     */
 
-    vm->host.initialized = 1; // monitor initialized and in OK state.
-    return(0); // all OK
+    vm->host.initialized = 1; /* monitor initialized and in OK state. */
+    return(0); 	/* all OK */
 
 error:
-    return(-1); // error in init_monitor()
+    return(-1); /* error in init_monitor() */
 }
 
-  static int
+
+static int
 init_idt_slot(vm_t *vm, unsigned vec, int type)
 /*
  *  init_idt_slot():  Initialize a monitor IDT slot.
@@ -424,18 +440,22 @@
     idt_stub_t *stub = &vm->host.addr.idt_stubs[vec];
     Bit32u handler_mon, stub_mon;
 
-    if (sizeof(idt_stub_t) != IDT_STUB_SIZE) {
-      return(-1);
-      }
+    if (sizeof(idt_stub_t) != IDT_STUB_SIZE)
+    {
+        return(-1);
+    }
 
-    // The handler and small stub (which calls the handler) addresses
-    // from the monitor's perspective.
+    /*
+     *  The handler and small stub (which calls the handler) addresses
+     *  from the monitor's perspective.
+     */
     handler_mon = type == IDT_INTERRUPT ? (Bit32u) MON_NEXUS_OFFSET(__guest2host)
                                         : (Bit32u) MON_NEXUS_OFFSET(__handle_fault);
     stub_mon = ((Bit32u) vm->guest.addr.idt_stubs) + vec*sizeof(idt_stub_t);
 
-    switch (type) {
-      case IDT_INTERRUPT:
+    switch (type)
+    {
+    case IDT_INTERRUPT:
         stub->m2.pushla = 0x68;
         stub->m2.dummy  = 0;
         stub->m2.pushlb = 0x68;
@@ -444,14 +464,16 @@
         stub->m2.reloc  = handler_mon -
           (stub_mon + sizeof(idt_method2_t));
         break;
-      case IDT_EXCEPTION_ERROR:
+
+    case IDT_EXCEPTION_ERROR:
         stub->m1.pushl  = 0x68;
         stub->m1.vector = vec;
         stub->m1.jmp    = 0xe9;
         stub->m1.reloc  = handler_mon -
           (stub_mon + sizeof(idt_method1_t));
         break;
-      case IDT_EXCEPTION_NOERROR:
+
+    case IDT_EXCEPTION_NOERROR:
         stub->m2.pushla = 0x68;
         stub->m2.dummy  = 0;
         stub->m2.pushlb = 0x68;
@@ -460,9 +482,10 @@
         stub->m2.reloc  = handler_mon -
           (stub_mon + sizeof(idt_method2_t));
         break;
-      default:
+
+    default:
         return(-1);
-      }
+    }
 
     /* Set the interrupt gate */
     SET_INT_GATE(vm->host.addr.idt[vec],
@@ -470,7 +493,8 @@
     return(0);
 }
 
-  static void
+
+static void
 map_monitor(vm_t *vm)
 /*
  *  map_monitor():  Map monitor into monitor/guest environment.
@@ -493,7 +517,7 @@
     Bit32u laddr, base;
     int i;
 
-    // Search for unused GDT selectors
+    /* Search for unused GDT selectors */
     for ( i = 1; i < MON_GDT_PAGES*PAGESIZE/8; i++ )
         if (    ((Bit32u *)&vm->host.addr.gdt[i])[0] == 0
              && ((Bit32u *)&vm->host.addr.gdt[i])[1] == 0 )
@@ -501,6 +525,7 @@
             cs = i << 3;
             break;
         }
+
     for ( i++; i < MON_GDT_PAGES*PAGESIZE/8; i++ )
         if (    ((Bit32u *)&vm->host.addr.gdt[i])[0] == 0
              && ((Bit32u *)&vm->host.addr.gdt[i])[1] == 0 )
@@ -508,6 +533,7 @@
             ss = i << 3;
             break;
         }
+
     for ( i++; i < MON_GDT_PAGES*PAGESIZE/8; i++ )
         if (    ((Bit32u *)&vm->host.addr.gdt[i])[0] == 0
              && ((Bit32u *)&vm->host.addr.gdt[i])[1] == 0 )
@@ -515,20 +541,21 @@
             tss = i << 3;
             break;
         }
+
     if ( !cs || !ss || !tss )
     {
         vm->host.initialized = 0;
         return;
     }
 
-    // Search for unused PDE for nexus PT  (fixed for now)
+    /* Search for unused PDE for nexus PT  (fixed for now) */
     laddr = 0x80000000;
     base  = MON_BASE_FROM_LADDR(laddr);
 
-    // Map nexus into monitor/guest address space
+    /* Map nexus into monitor/guest address space */
     vm->host.addr.page_dir[laddr >> 22] = vm->host.nexus_pde;
 
-    // Set up monitor GDT descriptors
+    /* Set up monitor GDT descriptors */
     SET_DESCRIPTOR(vm->host.addr.gdt[cs >> 3], base, 0xfffff, 
                    D_PG, D_D32, D_AVL0, D_PRESENT, D_DPL0, D_CODE | D_READ)
     SET_DESCRIPTOR(vm->host.addr.gdt[ss >> 3], base, 0xfffff, 
@@ -538,39 +565,40 @@
                    sizeof(tss_t)-1,
                    D_BG, 0, D_AVL0, D_PRESENT, D_DPL0, D_TSS)
 
-    // Fix up the selectors of all IDT entries
+    /* Fix up the selectors of all IDT entries */
     for ( i = 0; i < 256; i++ )
         vm->host.addr.idt[i].selector = cs;
 
-    // The monitor GDT/IDT loading info
-//vm->host.addr.nexus->mon_gdt_info.base  = base + vm->host.addr.nexus->gdt_offset;
+    /* The monitor GDT/IDT loading info */
+//  vm->host.addr.nexus->mon_gdt_info.base  = base + vm->host.addr.nexus->gdt_offset;
     vm->host.addr.nexus->mon_gdt_info.base  = base + (Bit32u) vm->guest.addr.gdt;
     vm->host.addr.nexus->mon_gdt_info.limit = 0xffff; // MON_GDT_SIZE; // +++
     vm->host.addr.nexus->mon_idt_info.base  = base + (Bit32u) vm->guest.addr.idt;
     vm->host.addr.nexus->mon_idt_info.limit = 0xffff; // MON_IDT_SIZE; // +++
 
-    // We don't have a monitor LDT for now
+    /* We don't have a monitor LDT for now */
     vm->host.addr.nexus->mon_ldt_sel = 0;
 
-    // The monitor TSS
+    /* The monitor TSS */
     vm->host.addr.nexus->mon_tss_sel = tss;
     vm->host.addr.tss->esp0 = ((Bit32u)vm->guest.addr.nexus) + PAGESIZE;
     vm->host.addr.tss->ss0  = ss;
 
-    // Monitor code and stack info
+    /* Monitor code and stack info */
     vm->host.addr.nexus->mon_jmp_info.offset     = MON_NEXUS_OFFSET(__mon_cs);
     vm->host.addr.nexus->mon_jmp_info.selector   = cs;
     vm->host.addr.nexus->mon_stack_info.offset   = vm->host.addr.tss->esp0 - sizeof(guest_context_t);
     vm->host.addr.nexus->mon_stack_info.selector = vm->host.addr.tss->ss0;
 
-    // Monitor PDBR
+    /* Monitor PDBR */
     vm->host.addr.nexus->mon_cr3 = vm->common.pages.page_dir << 12;
 
-    // Monitor code/data segment base
+    /* Monitor code/data segment base */
     vm->host.addr.nexus->mon_base = base;
 }
 
-  static void
+
+static void
 unmap_monitor(vm_t *vm)
 /*
  *  unmap_monitor():  Unmap monitor from monitor/guest environment.
@@ -590,32 +618,36 @@
  *     none
  */
 {
-    // Retrieve monitor parameters
+    /* Retrieve monitor parameters */
     Bit16u cs    = vm->host.addr.nexus->mon_jmp_info.selector;
     Bit16u ss    = vm->host.addr.nexus->mon_stack_info.selector;
     Bit16u tss   = vm->host.addr.nexus->mon_tss_sel; 
     Bit32u base  = vm->host.addr.nexus->mon_base;
     Bit32u laddr = LADDR_FROM_MON_BASE(base);
 
-    // Unmap nexus from monitor/guest address space
+    /* Unmap nexus from monitor/guest address space */
     *(Bit32u *)&vm->host.addr.page_dir[laddr >> 22] = 0;
 
-    // Clear out monitor GDT descriptors
+    /* Clear out monitor GDT descriptors */
     SET_DESCRIPTOR(vm->host.addr.gdt[cs  >> 3], 0, 0, 0, 0, 0, 0, 0, 0)
     SET_DESCRIPTOR(vm->host.addr.gdt[ss  >> 3], 0, 0, 0, 0, 0, 0, 0, 0)
     SET_DESCRIPTOR(vm->host.addr.gdt[tss >> 3], 0, 0, 0, 0, 0, 0, 0, 0)
 }
 
 
-  void
+void
 host2guest(vm_t *vm)
 {
+    vm_t *vm_guest;
+
     for (;;)
     {
         if (!vm->host.initialized) 
         {
-            // Monitor not in an OK state to run.  Either it was not init'd,
-            // or an internal monitor error occurred previously.
+            /*
+             *  Monitor not in an OK state to run.  Either it was not init'd,
+             *  or an internal monitor error occurred previously.
+             */
             vm->host.guest_context->event_info = RET_BECAUSE_MON_ERROR<<8;
             return;
         }
@@ -624,35 +656,33 @@
         sbe_setup(vm);
 #endif
 
-{
-vm_t *vm_guest;
-//vm->common.addr = &vm->guest.addr;
-vm_guest = vm->host.addr.nexus->vm;
-vm->common.addr = &vm_guest->guest.addr;
-}
-
+//      vm->common.addr = &vm->guest.addr;
+        vm_guest = vm->host.addr.nexus->vm;
+        vm->common.addr = &vm_guest->guest.addr;
 
-        // Call assembly routine to effect transition.
+        /* Call assembly routine to effect transition. */
         vm->host.__host2guest();
 
-vm->common.addr = &vm->host.addr;
+        vm->common.addr = &vm->host.addr;
 
 #ifdef SBE
-        // Restore page mapping for current code page.  The TLB
-        // trick code mapped it to the private code page.
-        * vm->host.codepage_pte_p = vm->host.codepage_pte_saved;
+        /*
+         *  Restore page mapping for current code page.  The TLB
+         *  trick code mapped it to the private code page.
+         */
+        *vm->host.codepage_pte_p = vm->host.codepage_pte_saved;
 #endif
 
         switch ( (vm->host.guest_context->event_info >> 8) & 0xff )
         {
         default:
         case RET_BECAUSE_MON_ERROR:
-            // Kill VM if fatal monitor error occurred
+            /* Kill VM if fatal monitor error occurred */
             vm->host.initialized = 0;
             return;
 
         case RET_BECAUSE_REMAP:
-            // Re-map monitor into guest context and restart
+            /* Re-map monitor into guest context and restart */
             unmap_monitor(vm);
             map_monitor(vm);
             break;
@@ -660,7 +690,7 @@
         case RET_BECAUSE_REDIR:
         case RET_BECAUSE_EMERR:
         case RET_BECAUSE_USEREMU:
-            // Host needs to handle this situation
+            /* Host needs to handle this situation */
             return;
         }
     }
@@ -668,39 +698,45 @@
 
 
 
-// Map pages allocated by host, into the linear address space of
-// the monitor/guest, given the Page Table supplied.
+/*
+ *  Map pages allocated by host, into the linear address space of
+ *  the monitor/guest, given the Page Table supplied.
+ */
 
-  void
+void
 map_nexus_pages(Bit32u *pages, unsigned n, Bit32u *laddr_p, page_t *pageTable)
 {
-  unsigned i, pti;
+    unsigned i, pti;
 
-  pti = (*laddr_p >> 12) & 0x3ff;
-  for (i = 0; i < n; i++, pti++) {
-    if (pti > 1024)
-        break;  // This should not happen!
+    pti = (*laddr_p >> 12) & 0x3ff;
+    for (i = 0; i < n; i++, pti++)
+    {
+        if (pti > 1024)
+            break;  /* This should not happen! */
 
-    // Fill in the PTE flags
-    pageTable->u.pte[pti].base = pages[i];
-    pageTable->u.pte[pti].avail = 0;
-    pageTable->u.pte[pti].G = 0;      // not global
-    pageTable->u.pte[pti].PS = 0;     // (unused in pte)
-    pageTable->u.pte[pti].D = 0;      // clean
-    pageTable->u.pte[pti].A = 0;      // not accessed
-    pageTable->u.pte[pti].PCD = 0;    // normal caching
-    pageTable->u.pte[pti].PWT = 0;    // normal write-back
-    pageTable->u.pte[pti].US = 0;     // user *cannot* access
-    pageTable->u.pte[pti].RW = 1;     // read or write
-    pageTable->u.pte[pti].P = 1;      // present in memory
+        /* Fill in the PTE flags */
+        pageTable->u.pte[pti].base = pages[i];
+        pageTable->u.pte[pti].avail = 0;
+        pageTable->u.pte[pti].G = 0;      /* not global			*/
+        pageTable->u.pte[pti].PS = 0;     /* (unused in pte)		*/
+        pageTable->u.pte[pti].D = 0;      /* clean			*/
+        pageTable->u.pte[pti].A = 0;      /* not accessed		*/
+        pageTable->u.pte[pti].PCD = 0;    /* normal caching		*/
+        pageTable->u.pte[pti].PWT = 0;    /* normal write-back		*/
+        pageTable->u.pte[pti].US = 0;     /* user *cannot* access	*/
+        pageTable->u.pte[pti].RW = 1;     /* read or write		*/
+        pageTable->u.pte[pti].P = 1;      /* present in memory		*/
     }
 
-  // Advance linear address pointer, for the next set of pages
-  // to be mapped.
-  *laddr_p += 4096 * n;
+    /*
+     *  Advance linear address pointer, for the next set of pages
+     *  to be mapped.
+     */
+    *laddr_p += 4096 * n;
 }
 
-  void
+
+void
 set_guest_context( vm_t *vm, guest_context_t *context )
 /*
  *  set_guest_context():  Set the current guest context
@@ -738,7 +774,8 @@
                                           vm->host.addr.nexus->mon_eflags);
 }
 
-  void
+
+void
 get_guest_context( vm_t *vm, guest_context_t *context )
 /*
  *  get_guest_context():  Get the current guest context
@@ -753,7 +790,7 @@
 }
 
 
-  void
+void
 virtualize_guest_paging(vm_t *vm)
 {
     unsigned pdi, pti, page_index;
@@ -767,124 +804,139 @@
      *  at the lower end of the virtual address space.
      */
 
-    // Actually, I need to modify this code to handle virtualizing
-    // guest page tables (or creating an identity map if paging
-    // is not enabled) any time there is a PDBR change or at
-    // initialization time.  -kpl
+    /*
+     *  Actually, I need to modify this code to handle virtualizing
+     *  guest page tables (or creating an identity map if paging
+     *  is not enabled) any time there is a PDBR change or at
+     *  initialization time.  -kpl
+     */
 
     page_index = 0;
     for (pdi=0; pdi<(vm->common.pages.guest_n_megs>>2); pdi++) 
     {
-        // Fill in the PDE flags
+        /* Fill in the PDE flags */
 
-        // Get the address of the page table
+        /* Get the address of the page table */
         vm->host.addr.page_dir[pdi].base = vm->common.pages.page_tbl[pdi];
         vm->host.addr.page_dir[pdi].avail = 0;
-        vm->host.addr.page_dir[pdi].G = 0;      // not global
-        vm->host.addr.page_dir[pdi].PS = 0;     // 4K pages
-        vm->host.addr.page_dir[pdi].D = 0;      // (unused in pde)
-        vm->host.addr.page_dir[pdi].A = 0;      // not accessed
-        vm->host.addr.page_dir[pdi].PCD = 0;    // normal caching
-        vm->host.addr.page_dir[pdi].PWT = 0;    // normal write-back
-        vm->host.addr.page_dir[pdi].US = 1;     // user can access
-        vm->host.addr.page_dir[pdi].RW = 1;     // read or write
-        vm->host.addr.page_dir[pdi].P = 1;      // present in memory
+        vm->host.addr.page_dir[pdi].G = 0;      /* not global		*/
+        vm->host.addr.page_dir[pdi].PS = 0;     /* 4K pages		*/
+        vm->host.addr.page_dir[pdi].D = 0;      /* (unused in pde)	*/
+        vm->host.addr.page_dir[pdi].A = 0;      /* not accessed		*/
+        vm->host.addr.page_dir[pdi].PCD = 0;    /* normal caching	*/
+        vm->host.addr.page_dir[pdi].PWT = 0;    /* normal write-back	*/
+        vm->host.addr.page_dir[pdi].US = 1;     /* user can access	*/
+        vm->host.addr.page_dir[pdi].RW = 1;     /* read or write	*/
+        vm->host.addr.page_dir[pdi].P = 1;      /* present in memory	*/
   
-        // clear Page Table
+        /* clear Page Table */
         pageTable = &vm->host.addr.page_tbl[pdi];
         zero_memory(pageTable, 4096);
   
-        // Setup the page table
+        /* Setup the page table */
         for (pti=0; pti<1024; pti++) 
         {
-            // Fill in the PTE flags
+            /* Fill in the PTE flags */
 
-            // Get the address of the page frame
+            /* Get the address of the page frame */
             pageTable->u.pte[pti].base = vm->common.pages.guest[page_index];
             page_index++;
             pageTable->u.pte[pti].avail = 0;
-            pageTable->u.pte[pti].G = 0;      // not global
-            pageTable->u.pte[pti].PS = 0;     // (unused in pte)
-            pageTable->u.pte[pti].D = 0;      // clean
-            pageTable->u.pte[pti].A = 0;      // not accessed
-            pageTable->u.pte[pti].PCD = 0;    // normal caching
-            pageTable->u.pte[pti].PWT = 0;    // normal write-back
-            pageTable->u.pte[pti].US = 1;     // user can access
-            pageTable->u.pte[pti].RW = 1;     // read or write
-            pageTable->u.pte[pti].P = 1;      // present in memory
+            pageTable->u.pte[pti].G = 0;      /* not global		*/
+            pageTable->u.pte[pti].PS = 0;     /* (unused in pte)	*/
+            pageTable->u.pte[pti].D = 0;      /* clean			*/
+            pageTable->u.pte[pti].A = 0;      /* not accessed		*/
+            pageTable->u.pte[pti].PCD = 0;    /* normal caching		*/
+            pageTable->u.pte[pti].PWT = 0;    /* normal write-back	*/
+            pageTable->u.pte[pti].US = 1;     /* user can access	*/
+            pageTable->u.pte[pti].RW = 1;     /* read or write		*/
+            pageTable->u.pte[pti].P = 1;      /* present in memory	*/
         }
     }
 }
 
 
 #ifdef SBE
-// This is some framework needed before the transition via
-// the nexus code occurs, when using SBE.  I still need to clean
-// up so that it can execute in either host or monitor address space.
+/*
+ *  This is some framework needed before the transition via
+ *  the nexus code occurs, when using SBE.  I still need to clean
+ *  up so that it can execute in either host or monitor address space.
+ */
 
-  void
-sbe_setup(vm_t *vm)
-{
-// Macros to get the fields from the guest CS descriptor.
+/* Macros to get the fields from the guest CS descriptor. */
 #define GET_CS_BASE() 0
 #define GET_CS_D()    1
 #define GET_CS_CPL()  0
 
-  Bit32u laddr, guest_laddr, guest_paddr;
-  unsigned seg32;
-  unsigned cpl;
-  unsigned icache_index;
-  unsigned pdi, pti;
-  pageEntry_t  pte_new;
-
-  guest_laddr = GET_CS_BASE() + vm->host.guest_context->eip;
-  guest_paddr = guest_laddr; // No paging supported yet, identity map
-// +++ physical mem boundary check here
-  //KPRINTF("plex86: it %u @ 0x%x\n", h2gcount, guest_paddr);
-  seg32 = GET_CS_D();
-  cpl = GET_CS_CPL();
-  icache_index = prescan(vm, guest_paddr, seg32, cpl, &opcode_vmap2, 1);
-
-  //
-  // Prepare for the split I&D TLB trick, mostly implemented
-  // in the nexus code.
-  //
-
-  // Store linear address of real code page and the address of the
-  // corresponding PTE, for use in the nexus code.
-  laddr = guest_laddr & 0xfffff000;
-  pdi = laddr >> 22;
-  pti = (laddr >> 12) & 0x3ff;
-  vm->common.addr->nexus->codepage_laddr =
-    laddr - vm->common.addr->nexus->mon_base;
-  vm->common.addr->nexus->codepage_pte_p = (pageEntry_t *)
-    (((Bit32u)vm->guest.addr.page_tbl) + (pdi<<12) + (pti<<2));
-  vm->host.codepage_pte_p = &vm->host.addr.page_tbl[pdi].u.pte[pti]; // host address
-
-  // Store the linear address of the virtualized code page, for
-  // use in the nexus code.
-  laddr = ((Bit32u)vm->guest.addr.icache) + (icache_index<<12);
-  vm->common.addr->nexus->private_codepage_laddr = laddr;
-
-  // Save current mapping of actual code page, then map it to
-  // the virtualized code page.  The nexus code uses this
-  // mapping to load the I TLB cache, before setting the PTE
-  // value to inaccessible so the D TLB cache load will trap.
-  vm->host.codepage_pte_saved = * vm->host.codepage_pte_p;
-  pte_new.base = vm->common.pages.icache[icache_index];
-  pte_new.avail = 0;
-  pte_new.G = 0;      // not global
-  pte_new.PS = 0;     // (unused in pte)
-  pte_new.D = 0;      // clean
-  pte_new.A = 0;      // not accessed
-  pte_new.PCD = 0;    // normal caching
-  pte_new.PWT = 0;    // normal write-back
-  pte_new.US = 1;     // user
-  pte_new.RW = 0;     // read-only
-  pte_new.P = 1;      // present in memory
-  * vm->host.codepage_pte_p = pte_new;
+void
+sbe_setup(vm_t *vm)
+{
+    Bit32u laddr, guest_laddr, guest_paddr;
+    unsigned seg32;
+    unsigned cpl;
+    unsigned icache_index;
+    unsigned pdi, pti;
+    pageEntry_t  pte_new;
+
+    guest_laddr = GET_CS_BASE() + vm->host.guest_context->eip;
+    guest_paddr = guest_laddr;	/* No paging supported yet, identity map */
+
+    /* +++ physical mem boundary check here */
+
+//  KPRINTF("plex86: it %u @ 0x%x\n", h2gcount, guest_paddr);
+
+    seg32 = GET_CS_D();
+    cpl = GET_CS_CPL();
+    icache_index = prescan(vm, guest_paddr, seg32, cpl, &opcode_vmap2, 1);
+
+    /*
+     *  Prepare for the split I&D TLB trick, mostly implemented
+     *  in the nexus code.
+     */
+
+    /*
+     *  Store linear address of real code page and the address of the
+     *  corresponding PTE, for use in the nexus code.
+     */
+    laddr = guest_laddr & 0xfffff000;
+    pdi = laddr >> 22;
+    pti = (laddr >> 12) & 0x3ff;
+    vm->common.addr->nexus->codepage_laddr =
+        laddr - vm->common.addr->nexus->mon_base;
+    vm->common.addr->nexus->codepage_pte_p = (pageEntry_t *)
+        (((Bit32u)vm->guest.addr.page_tbl) + (pdi<<12) + (pti<<2));
+    vm->host.codepage_pte_p =
+        &vm->host.addr.page_tbl[pdi].u.pte[pti]; /* host address */
+
+    /*
+     *  Store the linear address of the virtualized code page, for
+     *  use in the nexus code.
+     */
+    laddr = ((Bit32u)vm->guest.addr.icache) + (icache_index<<12);
+    vm->common.addr->nexus->private_codepage_laddr = laddr;
 
-  // Update timestamp for latest time of guest execution
-  vm->common.code_cache[icache_index].ts.guest_executed = rdtsc();
+    /*
+     *  Save current mapping of actual code page, then map it to
+     *  the virtualized code page.  The nexus code uses this
+     *  mapping to load the I TLB cache, before setting the PTE
+     *  value to inaccessible so the D TLB cache load will trap.
+     */
+    vm->host.codepage_pte_saved = * vm->host.codepage_pte_p;
+    pte_new.base = vm->common.pages.icache[icache_index];
+    pte_new.avail = 0;
+    pte_new.G = 0;      /* not global		*/
+    pte_new.PS = 0;     /* (unused in pte)	*/
+    pte_new.D = 0;      /* clean		*/
+    pte_new.A = 0;      /* not accessed		*/
+    pte_new.PCD = 0;    /* normal caching	*/
+    pte_new.PWT = 0;    /* normal write-back	*/
+    pte_new.US = 1;     /* user			*/
+    pte_new.RW = 0;     /* read-only		*/
+    pte_new.P = 1;      /* present in memory	*/
+    *vm->host.codepage_pte_p = pte_new;
+
+    /* Update timestamp for latest time of guest execution */
+    vm->common.code_cache[icache_index].ts.guest_executed = rdtsc();
 }
-#endif  // #ifdef SBE
+
+#endif  /* #ifdef SBE */
diff -Nur plex86-old/kernel/prescan.c plex86/kernel/prescan.c
--- plex86-old/kernel/prescan.c	Sun Mar 26 18:52:47 2000
+++ plex86/kernel/prescan.c	Sat Apr  1 14:27:20 2000
@@ -21,454 +21,476 @@
  */
 
 
-
 #include "plex86.h"
 #include "monitor.h"
 #include "prescan.h"
 
 
 #if 0
-// For printing debug spew
-static unsigned char *segnames[9] = {
-  "ES", "CS", "SS", "DS", "FS", "GS", "??", "??", "??"
-   };
+/* For printing debug spew */
+static unsigned char *segnames[9] =
+{
+    "ES", "CS", "SS", "DS", "FS", "GS", "??", "??", "??"
+};
 #endif
 
-// For debugging; see how many instructions were fetched in total.
+
+/* For debugging; see how many instructions were fetched in total. */
 static unsigned fetch_count_all = 0;
 static unsigned fetch_count_good = 0;
 
 
-// Shorthand macro
+/* Shorthand macro */
 #define RN OpcodeRunNative
 
-// Define a virtualization opcode map.  The shorthand macro 'RN'
-// means Run Natively.  '0' means virtualize.  First, define
-// entries for the one and then two byte x86 opcodes.  Then
-// define entries for the special opcode groups.
 
-opcode_vmap_t opcode_vmap = {
-{
-// 0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F
-  // 1-byte opcodes
-  RN, RN, RN, RN, RN, RN,  0,  0, RN, RN, RN, RN, RN, RN,  0,  0, // 00..0F
-  RN, RN, RN, RN, RN, RN,  0,  0, RN, RN, RN, RN, RN, RN,  0,  0, // 10..1F
-  RN, RN, RN, RN, RN, RN,  0, RN, RN, RN, RN, RN, RN, RN,  0, RN, // 20..2F
-  RN, RN, RN, RN, RN, RN,  0, RN, RN, RN, RN, RN, RN, RN,  0, RN, // 30..3F
-  RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, // 40..4F
-  RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, // 50..5F
-  RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, // 60..6F
-  RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, // 70..7F
-  RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN,  0,  0,  0, RN, // 80..8F
-  RN, RN, RN, RN, RN, RN, RN, RN, RN, RN,  0, RN,  0,  0, RN, RN, // 90..9F
-  RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, // A0..AF
-  RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, // B0..BF
-  RN, RN,  0,  0,  0,  0, RN, RN,  0,  0,  0,  0,  0,  0,  0,  0, // C0..CF
-  RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, // D0..DF
-  RN, RN, RN, RN,  0,  0,  0,  0, RN, RN,  0, RN,  0,  0,  0,  0, // E0..EF
-  RN,  0, RN, RN,  0, RN, RN, RN, RN, RN,  0,  0, RN, RN, RN, RN, // F0..FF
-
-  // 2-byte opcodes
-  RN, RN,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0, // 00..0F
-   0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0, // 10..1F
-   0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0, // 20..2F
-   0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0, // 30..3F
-   0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0, // 40..4F
-   0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0, // 50..5F
-   0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0, // 60..6F
-   0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0, // 70..7F
-
-  RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, // 80..8F
-  RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, // 90..9F
-   0,  0,  0, RN, RN, RN,  0,  0,  0,  0,  0, RN, RN, RN,  0, RN, // A0..AF
-   0,  0,  0, RN,  0,  0, RN, RN,  0,  0, RN, RN, RN, RN, RN, RN, // B0..BF
-   0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0, // C0..CF
-   0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0, // D0..DF
-   0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0, // E0..EF
-   0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0, // F0..FF
-},
+/*
+ *  Define a virtualization opcode map.  The shorthand macro 'RN'
+ *  means Run Natively.  '0' means virtualize.  First, define
+ *  entries for the one and then two byte x86 opcodes.  Then
+ *  define entries for the special opcode groups.
+ */
+
+opcode_vmap_t opcode_vmap =
 {
- {RN, RN, RN, RN, RN, RN, RN, RN}, // G1EbIb
- {RN, RN, RN, RN, RN, RN, RN, RN}, // G1Ew
- {RN, RN, RN, RN, RN, RN, RN, RN}, // G1Ed
- {RN, RN, RN, RN, RN, RN, RN, RN}, // G2Eb
- {RN, RN, RN, RN, RN, RN, RN, RN}, // G2Ew
- {RN, RN, RN, RN, RN, RN, RN, RN}, // G2Ed
- {RN, RN, RN, RN, RN, RN, RN, RN}, // G3Eb
- {RN, RN, RN, RN, RN, RN, RN, RN}, // G3Ew
- {RN, RN, RN, RN, RN, RN, RN, RN}, // G3Ed
- {RN, RN,  0,  0,  0,  0,  0,  0}, // G4
- {RN, RN,  0,  0,  0,  0, RN,  0}, // G5w
- {RN, RN,  0,  0,  0,  0, RN,  0}, // G5d
- { 0,  0,  0,  0,  0,  0,  0,  0}, // G6
- { 0,  0,  0,  0,  0,  0,  0,  0}, // G7
- { 0,  0,  0,  0, RN, RN, RN, RN}, // G8EvIb
- { 0,  0,  0,  0,  0,  0,  0,  0}  // G9
-}
+    {
+/******************************* 1-byte opcodes ******************************/
+/*            0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F  */
+/*****************************************************************************/
+/* 00..0F */  RN, RN, RN, RN, RN, RN, 0,  0,  RN, RN, RN, RN, RN, RN, 0,  0,
+/* 10..1F */  RN, RN, RN, RN, RN, RN, 0,  0,  RN, RN, RN, RN, RN, RN, 0,  0,
+/* 20..2F */  RN, RN, RN, RN, RN, RN, 0,  RN, RN, RN, RN, RN, RN, RN, 0,  RN,
+/* 30..3F */  RN, RN, RN, RN, RN, RN, 0,  RN, RN, RN, RN, RN, RN, RN, 0,  RN,
+/* 40..4F */  RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN,
+/* 50..5F */  RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN,
+/* 60..6F */  RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN,
+/* 70..7F */  RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN,
+/* 80..8F */  RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, 0,  0,  0,  RN,
+/* 90..9F */  RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, 0,  RN, 0,  0,  RN, RN,
+/* A0..AF */  RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN,
+/* B0..BF */  RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN,
+/* C0..CF */  RN, RN, 0,  0,  0,  0,  RN, RN, 0,  0,  0,  0,  0,  0,  0,  0,
+/* D0..DF */  RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN,
+/* E0..EF */  RN, RN, RN, RN, 0,  0,  0,  0,  RN, RN, 0,  RN, 0,  0,  0,  0,
+/* F0..FF */  RN, 0,  RN, RN, 0,  RN, RN, RN, RN, RN, 0,  0,  RN, RN, RN, RN,
+/*****************************************************************************/
+
+/******************************* 2-byte opcodes ******************************/
+/*            0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F  */
+/*****************************************************************************/
+/* 00..0F */  RN, RN, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
+/* 10..1F */  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
+/* 20..2F */  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
+/* 30..3F */  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
+/* 40..4F */  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
+/* 50..5F */  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
+/* 60..6F */  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
+/* 70..7F */  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
+/* 80..8F */  RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN,
+/* 90..9F */  RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN, RN,
+/* A0..AF */  0,  0,  0,  RN, RN, RN, 0,  0,  0,  0,  0,  RN, RN, RN, 0,  RN,
+/* B0..BF */  0,  0,  0,  RN, 0,  0,  RN, RN, 0,  0,  RN, RN, RN, RN, RN, RN,
+/* C0..CF */  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
+/* D0..DF */  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
+/* E0..EF */  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
+/* F0..FF */  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
+/*****************************************************************************/
+    },
+    {
+	{ RN, RN, RN, RN, RN, RN, RN, RN },	/* G1EbIb  */
+	{ RN, RN, RN, RN, RN, RN, RN, RN },	/* G1Ew    */
+	{ RN, RN, RN, RN, RN, RN, RN, RN },	/* G1Ed    */
+	{ RN, RN, RN, RN, RN, RN, RN, RN },	/* G2Eb    */
+	{ RN, RN, RN, RN, RN, RN, RN, RN },	/* G2Ew    */
+	{ RN, RN, RN, RN, RN, RN, RN, RN },	/* G2Ed    */
+	{ RN, RN, RN, RN, RN, RN, RN, RN },	/* G3Eb    */
+	{ RN, RN, RN, RN, RN, RN, RN, RN },	/* G3Ew    */
+	{ RN, RN, RN, RN, RN, RN, RN, RN },	/* G3Ed    */
+	{ RN, RN, 0,  0,  0,  0,  0,  0  },	/* G4      */
+	{ RN, RN, 0,  0,  0,  0,  RN, 0  },	/* G5w     */
+	{ RN, RN, 0,  0,  0,  0,  RN, 0  },	/* G5d     */
+	{ 0,  0,  0,  0,  0,  0,  0,  0  },	/* G6      */
+	{ 0,  0,  0,  0,  0,  0,  0,  0  },	/* G7      */
+	{ 0,  0,  0,  0,  RN, RN, RN, RN },	/* G8EvIb  */
+	{ 0,  0,  0,  0,  0,  0,  0,  0  },	/* G9      */
+    }
 };
 
-// Some special cases I've noted for whatever reasons.
-//   push esp, pop esp? 54, 5c
-//   cmov 0f 40..4f
-//   cmpxchg_xbts/ibts 0f a6/a7
-//   cmpxchg_e.g. 0f b0/b1
-//   xadd_e.g. 0f c0/c1
-//   group9 0f c7
-//   bswap_e.x 0f c8..cf
-//   group9 0f c7 nnn=1
-
-
-#if 0
-  int
-main(int argc, char *argv[])
+/*  Some special cases I've noted for whatever reasons. (Kevin)
+ *    push esp, pop esp? 54, 5c
+ *    cmov 0f 40..4f
+ *    cmpxchg_xbts/ibts 0f a6/a7
+ *    cmpxchg_e.g. 0f b0/b1
+ *    xadd_e.g. 0f c0/c1
+ *    group9 0f c7
+ *    bswap_e.x 0f c8..cf
+ *    group9 0f c7 nnn=1
+ */
+
+
+/*
+ *  Prescan guest code before it can be executed, starting at a
+ *  particular address.
+ *
+ *  What we do is _iterate_ through a code sequence until a
+ *  terminal condition is reached, and _recurse_ to branch
+ *  targets where possible.  For most instructions, we can
+ *  continue scanning the instruction that follows.  For
+ *  conditional branch instructions, we can possibly scan
+ *  both the following instruction, and the branch target.
+ *  For unconditional branches, we can only potentially scan
+ *  the branch target.
+ */
+
+unsigned
+prescan (vm_t * vm, Bit32u paddr, unsigned seg32, unsigned cpl,
+	 opcode_vmap_t * op_vmap, unsigned depth)
 {
-  //unsigned char *p;
-  Bit32u offset, paddr;
-  int fd;
-  unsigned seg32, cpl;
-  code_cache_entry_t *cache_entry;
-
-  // Print out debug info; look at the aftermath of prescanning.
-
-  // Print out page info.
-  {
-  Bit64u ts;
-  printf("page[0] info:\n");
-  ts = cache_entry->ts.guest_read;
-  printf("  ts.guest_read:     %x:%08x\n", (Bit32u) (ts>>32), (u32) ts);
-  ts = cache_entry->ts.guest_write;
-  printf("  ts.guest_write:    %x:%08x\n", (Bit32u) (ts>>32), (u32) ts);
-  ts = cache_entry->ts.guest_executed;
-  printf("  ts.guest_executed: %x:%08x\n", (Bit32u) (ts>>32), (u32) ts);
-  ts = cache_entry->ts.mon_created;
-  printf("  ts.mon_created:    %x:%08x\n", (Bit32u) (ts>>32), (u32) ts);
-  ts = cache_entry->ts.mon_prescan;
-  printf("  ts.mon_prescan:    %x:%08x\n", (Bit32u) (ts>>32), (u32) ts);
-  printf("  seg32: %u\n", cache_entry->seg32);
-  printf("  cpl:  %u\n", cache_entry->cpl);
-  printf("\n");
-  }
-
-  // Print out the meta cache values to see if our algorithm worked,
-  // for the given case.  You might want to change this to your liking.
-  // I only print out information about offsets where something
-  // in the meta cache has been set.
-  {
-  unsigned i;
-  for (i=0; i<4096; i++) {
-    if (meta[i]) {
-      printf("offset:%u opcode:0x%02x meta:", i, virtualized[i]);
-      if (meta[i] & MetaOpcodeStart) printf("O");
-      else                           printf(".");
-
-      if (meta[i] & MetaOpcodeByte)  printf("o");
-      else                           printf(".");
-
-      if (meta[i] & MetaOpcodeStart) {
-        // only print native/virtualized if an opcode start
-        if (meta[i] & MetaRunNative)   printf("N");
-        else                           printf("V");
-        }
-      else
-        printf(".");
-
-      if (MetaGetILen(meta[i]))      printf("(%d)", MetaGetILen(meta[i]));
-      printf("\n");
-      }
-    }
-  printf("Key for meta information:\n");
-  printf("                     meta:xxx(x)\n");
-  printf("                          ||| +---- Opcode is this many bytes\n");
-  printf("                          |||\n");
-  printf("                          ||+------ N=Native, V=Virtualize\n");
-  printf("                          |+------- o=byte is part of an opcode\n");
-  printf("                          +-------- O=Opcode starts here\n");
-  }
-
-  // This is how many instructions were fetched.
-  printf("fetch_count_all  = %u\n", fetch_count_all);
-  printf("fetch_count_good = %u\n", fetch_count_good);
-
-  return(0);
-}
-#endif
-
+    unsigned ret;
+    instruction_t i;
+    unsigned vir_opcode_attr, immediate_type;
+    Bit32u page_boundary, max_len;
+    unsigned j, padding;
+    unsigned recurse_to_branch, iterate_to_next;
+    Bit32u offset;
+    Bit32u branch_offset;
+    code_cache_entry_t *cache_entry;
+    Bit32u page_bits;
+    unsigned icache_index;
+    page_t *virtualized_page_p;
+    page_t *meta_page_p;
+    Bit8u *actual_page_p;
+
+/* +++ bounds checks on paddr? */
+
+    page_bits = paddr & 0xfffff000;
+    offset = paddr & 0x00000fff;
+    icache_index = 0;			/* only 1 available for now */
+
+    cache_entry = &vm->common.code_cache[icache_index];	/* for now... */
+
+    virtualized_page_p = &vm->common.addr->icache[icache_index];
+    meta_page_p = &vm->common.addr->meta[icache_index];
+    actual_page_p = ((Bit8u *) vm->common.addr->guest) + page_bits;
+    branch_offset = 0;
+
+    if ((page_bits != cache_entry->guest_paddr) ||
+	(seg32 != cache_entry->seg32) ||
+	(cpl != cache_entry->cpl))
+    {
+	/* Address of actual code page in guest physical address space */
+	cache_entry->guest_paddr = page_bits;
+
+	/* Zero out code meta page */
+	zero_memory (meta_page_p, 4096);
+
+	/* Start private virtualized code page with copy of initial code page */
+	copy_memory (virtualized_page_p, actual_page_p, 4096);
+
+	cache_entry->seg32 = seg32;
+	cache_entry->cpl = cpl;
+	cache_entry->ts.mon_prescan =
+	cache_entry->ts.mon_created = rdtsc ();
+	cache_entry->ts.guest_read = 0;		/* Hasn't been read from yet  */
+	cache_entry->ts.guest_write = 0;	/* Hasn't been written to yet */
+    }
+    else
+    {
+	/*
+	 *  We have virtualized code in this page before.
+	 *  Only update mon_prescan timestamp, if we are going to
+	 *  modify something.
+	 */
+
+	if (!(meta_page_p->u.bytes[offset] & MetaOpcodeStart))
+	{
+	    cache_entry->ts.mon_prescan = rdtsc ();
+	}
+    }
+
+/* - segment base, base+limit within page?    */
+/* - make sure INT3 planted at all terminals  */
+
+//  KPRINTF("plex: paddr = 0x%x\n", paddr);
+
+  decode_next:
+
+    /*
+     *  If the current instruction has already been scanned, and
+     *  is marked in the meta cache, then we are done.
+     */
+
+    if (meta_page_p->u.bytes[offset] & MetaOpcodeStart)
+    {
+//	KPRINTF("TERMINAL: instruction already scanned\n");
+	return (icache_index);
+    }
+
+    /* Start out with the most common values. */
+    recurse_to_branch = 0;
+    iterate_to_next = 1;
+
+//  KPRINTF("plex: addr.guest = 0x%x\n", (unsigned) vm->common.addr->guest);
+//  KPRINTF("plex: host_laddr = 0x%x\n", (unsigned) actual_page_p);
+
+    page_boundary = offset | 0x00000fff;
+    max_len = (page_boundary - offset) + 1;
+    if (max_len > MaxIA32OpcodeLen)
+	max_len = MaxIA32OpcodeLen;	/* shorten to maximum x86 instruction length */
+//  KPRINTF("plex: max_len = %u\n", max_len);
 
-// Prescan guest code before it can be executed, starting at a
-// particular address.
-//
-// What I do is _iterate_ through a code sequence until a
-// terminal condition is reached, and _recurse_ to branch
-// targets where possible.  For most instructions, we can
-// continue scanning the instruction that follows.  For
-// conditional branch instructions, we can possibly scan
-// both the following instruction, and the branch target.
-// For unconditional branches, we can only potentially scan
-// the branch target.
-
-  unsigned
-prescan(vm_t *vm, Bit32u paddr, unsigned seg32, unsigned cpl,
-        opcode_vmap_t *op_vmap, unsigned depth)
-{
-  unsigned ret;
-  instruction_t i;
-  unsigned vir_opcode_attr, immediate_type;
-  Bit32u page_boundary, max_len;
-  unsigned j, padding;
-  unsigned recurse_to_branch, iterate_to_next;
-  Bit32u offset;
-  Bit32u branch_offset;
-  code_cache_entry_t *cache_entry;
-  Bit32u page_bits;
-  unsigned icache_index;
-  page_t  *virtualized_page_p;
-  page_t  *meta_page_p;
-  Bit8u      *actual_page_p;
-
-// +++ bounds checks on paddr?
-
-  page_bits = paddr & 0xfffff000;
-  offset    = paddr & 0x00000fff;
-  icache_index = 0; // only 1 available for now
-  cache_entry = &vm->common.code_cache[icache_index]; // for now...
-  virtualized_page_p = &vm->common.addr->icache[icache_index];
-  meta_page_p        = &vm->common.addr->meta[icache_index];
-  actual_page_p      = ((Bit8u *) vm->common.addr->guest) + page_bits;
-
-  if ( (page_bits != cache_entry->guest_paddr) ||
-       (seg32 != cache_entry->seg32) ||
-       (cpl   != cache_entry->cpl) ) {
-
-    // Address of actual code page in guest physical address space
-    cache_entry->guest_paddr = page_bits;
-
-    // Zero out code meta page
-    zero_memory(meta_page_p, 4096);
-    // Start private virtualized code page with copy of initial code page
-    copy_memory(virtualized_page_p, actual_page_p, 4096);
-
-    cache_entry->seg32 = seg32;
-    cache_entry->cpl   = cpl;
-    cache_entry->ts.mon_prescan =
-      cache_entry->ts.mon_created = rdtsc();
-    cache_entry->ts.guest_read  = 0; // Has not been read from yet.
-    cache_entry->ts.guest_write = 0; // Has not been written to yet.
-    }
-  else {
-    // We have virtualized code in this page before.
-    // Only update mon_prescan timestamp, if we are going to
-    // modify something.
-    if ( !(meta_page_p->u.bytes[offset] & MetaOpcodeStart) ) {
-      cache_entry->ts.mon_prescan = rdtsc();
-      }
-    }
-
-// - segment base, base+limit within page?
-// - make sure INT3 planted at all terminals
-
-//KPRINTF("plex: paddr = 0x%x\n", paddr);
-
-decode_next:
-
-  // If the current instruction has already been scanned, and
-  // is marked in the meta cache, then we are done.
-  if (meta_page_p->u.bytes[offset] & MetaOpcodeStart) {
-    //KPRINTF("TERMINAL: instruction already scanned\n");
-    return(icache_index);
-    }
-
-  // Start out with the most common values.
-  recurse_to_branch = 0;
-  iterate_to_next = 1;
-
-//KPRINTF("plex: addr.guest = 0x%x\n", (unsigned) vm->common.addr->guest);
-//KPRINTF("plex: host_laddr = 0x%x\n", (unsigned) actual_page_p);
-
-  page_boundary = offset | 0x00000fff;
-  max_len = (page_boundary - offset) + 1;
-  if (max_len > MaxIA32OpcodeLen)
-    max_len = MaxIA32OpcodeLen; // shorten to maximum x86 instruction length
-//KPRINTF("plex: max_len = %u\n", max_len);
-  ret = fetchDecode(&actual_page_p[offset], &i, max_len, seg32);
-fetch_count_all++; // counter for debug purposes
+    ret = fetchDecode (&actual_page_p[offset], &i, max_len, seg32);
+    fetch_count_all++;		/* counter for debug purposes */
 
 #if 0
-{
-static unsigned mecount=0;
-mecount++;
-if (mecount <= 20)
-  KPRINTF("plex: offset = 0x%x b1=0x%x\n", offset, i.b1);
-}
+    {
+	static unsigned mecount = 0;
+
+	mecount++;
+	if (mecount <= 20)
+	    KPRINTF ("plex: offset = 0x%x b1=0x%x\n", offset, i.b1);
+    }
 #endif
 
 #if 0
-  KPRINTF("ret=%u len=%u b1=0x%x inv=%u\n", ret, i.ilen, i.b1,
-    (i.attr & InvalidOpcode)>0);
-  KPRINTF("GroupN  = %u\n", (i.attr & GroupN)>0);
-  KPRINTF("seg   = 0x%x (%s)\n", i.seg, segnames[i.seg]);
-  KPRINTF("modrm   = 0x%x\n", i.modrm);
-  KPRINTF("  mod   = 0x%x\n", i.mod);
-  KPRINTF("  nnn   = 0x%x\n", i.nnn);
-  KPRINTF("   rm   = 0x%x\n", i.rm);
-  KPRINTF("sib     = 0x%x\n", i.sib);
-  KPRINTF("  scale = 0x%x\n", i.scale);
-  KPRINTF("  index = 0x%x\n", i.index);
-  KPRINTF("  base  = 0x%x\n", i.base);
+    KPRINTF ("ret=%u len=%u b1=0x%x inv=%u\n", ret, i.ilen, i.b1,
+	     (i.attr & InvalidOpcode) > 0);
+    KPRINTF ("GroupN  = %u\n", (i.attr & GroupN) > 0);
+    KPRINTF ("seg   = 0x%x (%s)\n", i.seg, segnames[i.seg]);
+    KPRINTF ("modrm   = 0x%x\n", i.modrm);
+    KPRINTF ("  mod   = 0x%x\n", i.mod);
+    KPRINTF ("  nnn   = 0x%x\n", i.nnn);
+    KPRINTF ("   rm   = 0x%x\n", i.rm);
+    KPRINTF ("sib     = 0x%x\n", i.sib);
+    KPRINTF ("  scale = 0x%x\n", i.scale);
+    KPRINTF ("  index = 0x%x\n", i.index);
+    KPRINTF ("  base  = 0x%x\n", i.base);
 #endif
 
+    /*
+     *  If fetch-decode ran up against a boundary and could not
+     *  fetch enough bytes, or if the opcode is invalid, then mark
+     *  the instruction as needing virtualization.
+     */
+
+    if ((ret == 0) || (i.attr & InvalidOpcode))
+    {
+//	KPRINTF("TERMINAL: fetch ran into boundary\n");
+	iterate_to_next = 0;
+	goto virtualize_instruction;
+    }
+
+    fetch_count_good++;		/* counter for debug purposes */
+
+    /*
+     *  Depending on whether opcode is a standard 1 or 2 byte opcode,
+     *  or one of the special groupN opcodes, get the virtualization
+     *  attributes from the virtualization opcode map.
+     */
+
+    if (i.attr & GroupN)
+    {
+	vir_opcode_attr = op_vmap->groups[GetGroupIndex (i.attr)][i.nnn];
+    }
+    else
+    {
+	vir_opcode_attr = op_vmap->standard[i.b1];
+    }
+//  KPRINTF("vir_opcode_attr = 0x%0x\n", vir_opcode_attr);
+
+    /*
+     *  We need to make sure that this instruction fits within the
+     *  page boundary, otherwise we have to virtualize it.
+     *  For most instructions, non-branch and conditional-branch,
+     *  execution of the following instruction is a possibility,
+     *  in which case we need to allow for one extra byte, so we
+     *  can virtualize the next instruction.  For unconditional
+     *  branches, we don't need this extra byte of padding.
+     */
+
+    padding = (i.attr & UCBranch) == 0;
+    if ((offset + i.ilen + padding) > 4096)
+    {
+//	KPRINTF("TERMINAL: instruction does not fit within page\n");
+	iterate_to_next = 0;
+	goto virtualize_instruction;
+    }
+
+    /*
+     *  If instruction was an unconditional relative branch, then
+     *  we do not need to iterate on the next instruction.
+     */
+
+    if (padding == 0)
+	iterate_to_next = 0;
+
+    /*
+     *  For relative branches, we need to look at the branch offset
+     *  to determine if this instruction can be run natively.  If it
+     *  branches within this page, then it can be run natively, otherwise
+     *  we must virtualize it.
+     */
+
+    immediate_type = i.attr & Immediate;
+
+    if ((immediate_type >= Immediate_BrOff8) &&
+	(immediate_type <= Immediate_BrOff32))
+    {
+	Bit32s opcode_offset;
+
+//	KPRINTF("### found Immediate_BrOffx (0x%x), off=%x\n", immediate_type, i.Id);
+
+	opcode_offset = i.Id;
+	branch_offset = (offset + i.ilen) + opcode_offset;
+
+//	KPRINTF("offset = 0x%x\n", offset);
+//	KPRINTF("i.ilen = %u\n", i.ilen);
+//	KPRINTF("opcode_offset = 0x%x\n", opcode_offset);
+
+	if (branch_offset >= 4096)
+	{
+	    /*
+             *  Relative branch to location out of page boundary; branch
+             *  needs to be virtualized.  We can, however, still iterate
+             *  on the next instruction if not an unconditional branch.
+	     */
+
+//	    KPRINTF("RelBranch: OOB (0x%x)\n", branch_offset);
+
+	    goto virtualize_instruction;
+	}
+	else
+	{
+	    /*
+             *  Branch within page boundaries.  We can recurse to the
+	     *  target branch address.
+             */
+
+//	    KPRINTF("RelBranch: OK (0x%x)\n", branch_offset);
+
+	    recurse_to_branch = 1;
+	}
+    }
+
+//  KPRINTF("RunNative = %u\n", (vir_opcode_attr & OpcodeRunNative)>0);
+
+    /*
+     *  We need to see if this instruction overlaps another instruction
+     *  which is virtualized.  If so, then we have no choice but to
+     *  virtualize this instruction, since the opcode bytes are changed.
+     *  Only bother looking if already marked to run native.
+     */
+
+    if (vir_opcode_attr & OpcodeRunNative)
+    {
+	for (j = 1; j < i.ilen; j++)
+	{
+	    if ((meta_page_p->u.bytes[offset + j] & (MetaOpcodeStart | MetaRunNative))
+		== MetaOpcodeStart)
+	    {
+		/*
+                 *  Overlap condition found.  In case our scanning has gotten
+		 *  thrown off track, stop iterating and recursing.  If this
+		 *  path is taken, we can resume scanning later when the
+		 *  breakpoint is encountered.
+		 */
+
+		recurse_to_branch = 0;
+		iterate_to_next = 0;
+		goto virtualize_instruction;
+	    }
+	}
+
+	/*
+         *  OK, circumstances are right so that we can let this
+	 *  instruction execute natively.
+         */
+
+	/*
+         *  Fill in meta cache entry, now that the instruction has been
+         *  decoded and we have the desired virtualization attributes set.
+         */
+
+	meta_page_p->u.bytes[offset] = MetaOpcodeStart | MetaOpcodeByte |
+	    MetaRunNative | i.ilen;
+
+	/* Mark the rest of the bytes involved in this instruction opcode. */
+	for (j = 1; j < i.ilen; j++)
+	{
+	    meta_page_p->u.bytes[offset + j] |= MetaOpcodeByte;
+	}
+    }
+    else
+    {
+	unsigned n;
+	Bit32u o;
+
+      virtualize_instruction:
+
+	/*
+         *  This instruction requires virtualization, normally or due
+	 *  to circumstances above.  We must insert a software breakpoint
+	 *  at the beginning of the instruction.  If by doing so, we step
+	 *  on any instructions before this one, which are not virtualized,
+	 *  we must mark them as requiring virtualization.  This is because
+	 *  we would be changing their opcode.  So we have to scan backwards
+	 *  and see if any instructions span this one.
+         */
+
+	/* Mark instruction as needing virtualization and with ilen==1 */
+	o = offset;
+	meta_page_p->u.bytes[o] = MetaOpcodeStart | MetaOpcodeByte | 1;
+	virtualized_page_p->u.bytes[o] = INT3;	/* insert software breakpoint */
+
+	n = 0;
+	while ((n < MaxIA32OpcodeLen) && o)
+	{
+	    o--;
+	    n++;
+	    if (((meta_page_p->u.bytes[o] & (MetaOpcodeStart | MetaRunNative)) ==
+		 (MetaOpcodeStart | MetaRunNative)) &&
+		(MetaGetILen (meta_page_p->u.bytes[o]) > n))
+	    {
+		/*
+                 *  Found the start of an instruction which has been scanned,
+		 *  is not virtualized, and spans the last modified instruction.
+		 *  Since we have to modify this instruction, we have to reset
+		 *  the counter and start the process over from here.
+                 */
+
+		/*  Insert software breakpoint */
+		virtualized_page_p->u.bytes[o] = INT3;
+		meta_page_p->u.bytes[o] &= ~MetaRunNative;
+		n = 0;
+	    }
+	}
+    }
+
+    if (recurse_to_branch && (depth < MAX_PRESCAN_DEPTH))
+    {
+	/*
+         *  If this is a conditional or unconditional branch to a
+	 *  static intrapage address, and we have not exceeded our
+	 *  maximum recursion depth, scan the code sequence at the
+	 *  branch target address.
+         */
 
-  // If fetch-decode ran up against a boundary and could not
-  // fetch enough bytes, or if the opcode is invalid, then mark
-  // the instruction as needing virtualization.
-  if ( (ret==0) || (i.attr & InvalidOpcode) ) {
-    //KPRINTF("TERMINAL: fetch ran into boundary\n");
-    iterate_to_next = 0;
-    goto virtualize_instruction;
-    }
-
-fetch_count_good++; // counter for debug purposes
-
-  // Depending on whether opcode is a standard 1 or 2 byte opcode,
-  // or one of the special groupN opcodes, get the virtualization
-  // attributes from the virtualization opcode map.
-  if (i.attr & GroupN) {
-    vir_opcode_attr = op_vmap->groups[GetGroupIndex(i.attr)][i.nnn];
-    }
-  else {
-    vir_opcode_attr = op_vmap->standard[i.b1];
-    }
-  //KPRINTF("vir_opcode_attr = 0x%0x\n", vir_opcode_attr);
-
-  // We need to make sure that this instruction fits within the
-  // page boundary, otherwise we have to virtualize it.
-  // For most instructions, non-branch and conditional-branch,
-  // execution of the following instruction is a possibility,
-  // in which case we need to allow for one extra byte, so we
-  // can virtualize the next instruction.  For unconditional
-  // branches, we don't need this extra byte of padding.
-  padding = (i.attr & UCBranch) == 0;
-  if ((offset + i.ilen + padding) > 4096) {
-    //KPRINTF("TERMINAL: instruction does not fit within page\n");
-    iterate_to_next = 0;
-    goto virtualize_instruction;
-    }
-  // If instruction was an unconditional relative branch, then
-  // we do not need to iterate on the next instruction.
-  if (padding==0)
-    iterate_to_next = 0;
-
-  // For relative branches, we need to look at the branch offset
-  // to determine if this instruction can be run natively.  If it
-  // branches within this page, then it can be run natively, otherwise
-  // we must virtualize it.
-  immediate_type = i.attr & Immediate;
-  if ( (immediate_type >= Immediate_BrOff8) &&
-       (immediate_type <= Immediate_BrOff32) ) {
-    Bit32s opcode_offset;
-    //KPRINTF("### found Immediate_BrOffx (0x%x), off=%x\n",
-    //     immediate_type, i.Id);
-    opcode_offset = i.Id;
-    branch_offset  = (offset + i.ilen) + opcode_offset;
-//KPRINTF("offset = 0x%x\n", offset);
-//KPRINTF("i.ilen = %u\n", i.ilen);
-//KPRINTF("opcode_offset = 0x%x\n", opcode_offset);
-    if (branch_offset >= 4096) {
-      // Relative branch to location out of page boundary; branch needs to
-      // be virtualized.  We can, however, still iterate on the next
-      // instruction if not an unconditional branch.
-      //KPRINTF("RelBranch: OOB (0x%x)\n", branch_offset);
-      goto virtualize_instruction;
-      }
-    else {
-      // Branch within page boundaries.  We can recurse to the
-      // target branch address.
-      //KPRINTF("RelBranch: OK (0x%x)\n", branch_offset);
-      recurse_to_branch = 1;
-      }
-    }
-  //KPRINTF("RunNative = %u\n", (vir_opcode_attr & OpcodeRunNative)>0);
-
-  // We need to see if this instruction overlaps another instruction
-  // which is virtualized.  If so, then we have no choice but to
-  // virtualize this instruction, since the opcode bytes are changed.
-  // Only bother looking if already marked to run native.
-  if (vir_opcode_attr & OpcodeRunNative) {
-    for (j=1; j<i.ilen; j++) {
-      if ((meta_page_p->u.bytes[offset+j] & (MetaOpcodeStart | MetaRunNative))
-          == MetaOpcodeStart) {
-        // Overlap condition found.  In case our scanning has gotten
-        // thrown off track, stop iterating and recursing.  If this
-        // path is taken, we can resume scanning later when the
-        // breakpoint is encountered.
-        recurse_to_branch = 0;
-        iterate_to_next = 0;
-        goto virtualize_instruction;
-        }
-      }
-
-    // OK, circumstances are right so that we can let this
-    // instruction execute natively.
-
-    // Fill in meta cache entry, now that the instruction has been decoded,
-    // and we have the desired virtualization attributes set.
-    meta_page_p->u.bytes[offset] = MetaOpcodeStart | MetaOpcodeByte |
-                   MetaRunNative | i.ilen;
-    // Mark the rest of the bytes involved in this instruction opcode.
-    for (j=1; j<i.ilen; j++) {
-      meta_page_p->u.bytes[offset+j] |= MetaOpcodeByte;
-      }
-    }
-  else {
-    unsigned n;
-    Bit32u o;
-
-virtualize_instruction:
-    // This instruction requires virtualization, normally or due
-    // to circumstances above.  We must insert a software breakpoint
-    // at the beginning of the instruction.  If by doing so, we step
-    // on any instructions before this one, which are not virtualized,
-    // we must mark them as requiring virtualization.  This is because
-    // we would be changing their opcode.  So we have to scan backwards
-    // and see if any instructions span this one.
-
-    // Mark instruction as needing virtualization and with ilen==1
-    o = offset;
-    meta_page_p->u.bytes[o] = MetaOpcodeStart | MetaOpcodeByte | 1;
-    virtualized_page_p->u.bytes[o] = INT3; // insert software breakpoint
-    n = 0;
-    while ((n<MaxIA32OpcodeLen) && o) {
-      o--;
-      n++;
-      if ( ((meta_page_p->u.bytes[o] & (MetaOpcodeStart | MetaRunNative)) ==
-            (MetaOpcodeStart | MetaRunNative)) &&
-           (MetaGetILen(meta_page_p->u.bytes[o]) > n) ) {
-        // Found the start of an instruction which has been scanned,
-        // is not virtualized, and spans the last modified instruction.
-        // Since we have to modify this instruction, we have to reset
-        // the counter and start the process over from here.
-        // Insert software breakpoint
-        virtualized_page_p->u.bytes[o] = INT3;
-        meta_page_p->u.bytes[o] &= ~MetaRunNative;
-        n = 0;
-        }
-      }
-    }
-
-  if (recurse_to_branch && (depth < MAX_PRESCAN_DEPTH)) {
-    // If this is a conditional or unconditional branch to a
-    // static intrapage address, and we have not exceeded our
-    // maximum recursion depth, scan the code sequence at the
-    // branch target address.
-    prescan(vm, page_bits | branch_offset, seg32, cpl, op_vmap, depth+1);
+	prescan (vm, page_bits | branch_offset, seg32, cpl, op_vmap, depth + 1);
     }
+
 #if 1
-  if (iterate_to_next) {
-    // Iterate scanning at next instruction.
-    offset += i.ilen;
-//KPRINTF("iterating to offset of 0x%x\n", offset);
-    goto decode_next;
+    if (iterate_to_next)
+    {
+	/* Iterate scanning at next instruction. */
+	offset += i.ilen;
+
+//      KPRINTF("iterating to offset of 0x%x\n", offset);
+
+	goto decode_next;
     }
 #endif
-  //KPRINTF("TERMINAL: iteration stops.\n");
-  return(icache_index);
+
+//  KPRINTF("TERMINAL: iteration stops.\n");
+
+    return (icache_index);
 }
