Another nit:
For an instruction like LGDT [modrm]
limit16 = [modrm]
base32 = [modrm+2]
or for that matter, any memory access which could span multiple
pages, I'm curious about the actual x86 behaviour WRT when
access checks and memory translations are peformed.
In the above example, one scenario might be:
- check that reading all 6 bytes of data is OK with segment permissions
- translate the addresses (DS.base + modrm) .. (DS.base + modrm + 5)
into 1 or 2 physical page addresses
- request all 6 bytes of data (via cache or data bus)
If this is the scenario used, then:
- If the data spans 2 pages, and if the 1st page is accessible
but the 2nd is not, is the page table for the 1st marked as
accessed? Is the data requested only if both pages are
accessible?
Or other scenario?
-Kevin
